PIC16F884-I/PT Microchip Technology, PIC16F884-I/PT Datasheet - Page 323

• Manufacturer Part Number: PIC16F884-I/PT
• Description: IC PIC MCU FLASH 4KX14 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F884-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: MSSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164120-2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC16
• Maximum Speed: 20 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPAC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timing Parameter Symbology........................................... 254
Timing Requirements
TRISA ................................................................................. 39
TRISA Register ................................................................... 39
TRISB ................................................................................. 47
TRISB Register ................................................................... 48
TRISC ................................................................................. 53
TRISC Register ................................................................... 53
TRISD ................................................................................. 57
© 2009 Microchip Technology Inc.
Bus Collision During a Stop Condition ...................... 207
Bus Collision for Transmit and Acknowledge............ 203
CLKOUT and I/O....................................................... 257
Clock Timing ............................................................. 255
Comparator Output ..................................................... 83
Enhanced Capture/Compare/PWM (ECCP) ............. 261
EUSART Synchronous Receive (Master/Slave) ....... 266
EUSART Synchronous Transmission
Fail-Safe Clock Monitor (FSCM) ................................. 72
Full-Bridge PWM Output ........................................... 137
Half-Bridge PWM Output .................................. 135, 144
I
I
I
I
I
I
INT Pin Interrupt........................................................ 222
Internal Oscillator Switch Timing................................. 68
Master Mode Transmit Clock Arbitration................... 202
PWM Auto-shutdown
PWM Direction Change ............................................ 138
PWM Direction Change at Near 100% Duty Cycle ... 139
PWM Output (Active-High)........................................ 133
PWM Output (Active-Low) ........................................ 134
Repeat Start Condition.............................................. 197
Reset, WDT, OST and Power-up Timer ................... 258
Send Break Character Sequence ............................. 170
Slave Synchronization .............................................. 186
SPI Master Mode (CKE = 1, SMP = 1) ..................... 267
SPI Mode Timing (Master Mode) SPI Mode
SPI Mode Timing (Slave Mode with CKE = 0) .......... 187
SPI Mode Timing (Slave Mode with CKE = 1) .......... 187
SPI Slave Mode (CKE = 0) ....................................... 268
SPI Slave Mode (CKE = 1) ....................................... 268
Stop Condition Receive or Transmit ......................... 202
Synchronous Reception (Master Mode, SREN) ....... 174
Synchronous Transmission....................................... 172
Synchronous Transmission (Through TXEN) ........... 172
Time-out Sequence
Timer0 and Timer1 External Clock ........................... 260
Timer1 Incrementing Edge.......................................... 78
Two Speed Start-up .................................................... 70
Wake-up from Interrupt ............................................. 227
I
I2C Bus Start/Stop Bits ............................................. 270
SPI Mode .................................................................. 269
2
2
2
2
2
2
2
C Bus Data ............................................................. 270
C Bus Start/Stop Bits.............................................. 269
C Master Mode First Start Bit Timing ..................... 196
C Master Mode Reception Timing.......................... 200
C Master Mode Transmission Timing..................... 199
C Module
C Bus Data ............................................................. 271
(Master/Slave) .................................................. 266
Bus Collision
Auto-restart Enabled ......................................... 143
Firmware Restart .............................................. 143
Master Mode Timing Diagram .......................... 185
Case 1 .............................................................. 216
Case 2 .............................................................. 216
Case 3 .............................................................. 216
Transmit Timing ........................................ 203
PIC16F882/883/884/886/887
TRISD Register................................................................... 57
TRISE ................................................................................. 59
TRISE Register................................................................... 59
Two-Speed Clock Start-up Mode........................................ 69
TXREG ............................................................................. 153
TXSTA Register................................................................ 160
U
Ultra Low-Power Wake-up................................ 16, 18, 40, 41
V
Voltage Reference (VR)
Voltage Reference. See Comparator
Voltage References
V
W
Wake-up on Break ............................................................ 168
Wake-up Using Interrupts ................................................. 226
Watchdog Timer (WDT).................................................... 224
Waveform for Slave Mode General Call
WCOL ............................................................... 196, 198, 201
WCOL Status Flag............................................ 196, 198, 201
WDTCON Register ........................................................... 225
WPUB Register................................................................... 49
WWW Address ................................................................. 323
WWW, On-Line Support ..................................................... 12
REF
BRGH Bit .................................................................. 163
Specifications ........................................................... 262
Voltage Reference (CV
Associated Registers.................................................. 97
VP6 Stabilization ........................................................ 94
. S
Associated Registers................................................ 225
Clock Source ............................................................ 224
Modes....................................................................... 224
Period ....................................................................... 224
Specifications ........................................................... 259
Address Sequence ................................................... 192
EE
ADC Reference Voltage
REF
)
DS41291F-page 321