ATTINY2313-20MU Atmel, ATTINY2313-20MU Datasheet - Page 55

• Manufacturer Part Number: ATTINY2313-20MU
• Description: IC MCU AVR 2K FLASH 20MLF
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI/UART/USI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 20MLF EP
• Device Core: AVR
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• For Use With: ATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: Q2312268A

2543L–AVR–08/10
Table 26. Overriding Signals for Alternate Functions in PB7..PB4
Table 27. Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PB7/USCK/
SCL/PCINT7
USI_TWO_WIRE
0
USI_TWO_WIRE
(USI_SCL_HOLD+
PORTB7)•DDB7
USI_TWO_WIRE •
DDB7
0
USI_PTOE
(PCINT7•PCIE)
+USISIE
1
PCINT7 INPUT
USCK INPUT SCL
INPUT
–
PB3/OC1A/
PCINT3
0
0
0
0
OC1A_PVOE
OC1A_PVOV
0
(PCINT3 • PCIE)
1
PCINT7 INPUT
–
PB6/DO/PCINT6
0
0
0
0
USI_THREE_WIRE
DO
0
(PCINT6•PCIE)
1
PCINT6 INPUT
–
PCINT6 INPUT
PB2/OC0A/
PCINT2
0
0
0
0
OC0A_PVOE
OC0A_PVOV
0
(PCINT2 • PCIE)
1
–
PB5/SDA/
DI/PCINT5
0
0
USI_TWO_WIRE
(SDA + PORTB5)•
DDB5
USI_TWO_WIRE
• DDB5
0
0
(PCINT5•PCIE) +
USISIE
1
PCINT5 INPUT
SDA INPUT
DI INPUT
–
PB1/AIN1/
PCINT1
0
0
0
0
0
0
0
(PCINT1 • PCIE)
1
PCINT5 INPUT
AIN1
PB4/OC1B/
PCINT4
0
0
0
0
OC1B_PVOE
0OC1B_PVOV
0
(PCINT4•PCIE)
1
PCINT4 INPUT
–
PB0/AIN0/
PCINT0
0
0
0
0
0
0
0
(PCINT0 • PCIE)
1
PCINT4 INPUT
AIN0
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