PIC18F44K20-I/PT Microchip Technology, PIC18F44K20-I/PT Datasheet - Page 341

IC PIC MCU FLASH 8KX16 44TQFP

PIC18F44K20-I/PT

Manufacturer Part Number
PIC18F44K20-I/PT
Description
IC PIC MCU FLASH 8KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F44K20-I/PT

Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Package
44TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Height
1 mm
Length
10 mm
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.8 V
Width
10 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20AC164305 - MODULE SKT FOR PM3 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F44K20-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44K20-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
NEGF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2008 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
Q1
=
=
register ‘f’
Negate f
NEGF
0 ≤ f ≤ 255
a ∈ [0,1]
( f ) + 1 → f
N, OV, C, DC, Z
Location ‘f’ is negated using two’s
complement. The result is placed in the
data memory location ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
NEGF
Read
0110
Q2
0011 1010 [3Ah]
1100 0110 [C6h]
f {,a}
REG, 1
110a
Process
Data
Q3
ffff
register ‘f’
Write
Q4
ffff
Preliminary
NOP
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
None.
PIC18F2XK20/4XK20
Q Cycle Activity:
Decode
Q1
operation
No Operation
NOP
None
No operation
None
No operation.
1
1
0000
1111
Q2
No
0000
xxxx
operation
Q3
No
DS41303D-page 339
0000
xxxx
operation
Q4
No
0000
xxxx

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