PIC16F627A-I/ML Microchip Technology, PIC16F627A-I/ML Datasheet - Page 2

• Manufacturer Part Number: PIC16F627A-I/ML
• Description: IC MCU FLASH 1KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627A-I/ML

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 20MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNI3DBF648 - BOARD DAUGHTER ICEPIC3AC164033 - ADAPTER 28QFN TO 18DIPAC162053 - HEADER INTERFACE ICD,ICD2 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16F627A-I/MLR; PIC16F627A-I/MLR

PIC16F627A/628A/648A
3. Module: Data EEPROM Memory
1.
The following example assumes that the desired
address is present in the EEADR register and the
desired data to be written is in the EEDATA register:
EXAMPLE 1:
DS80151N-page 2
BANKSEL 0X00
BCF
BANKSEL 0x80
MOVLW
MOVWF
MOVLW
MOVWF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
SLEEP
BCF
Note:
Note:
PIC16F648A Silicon revision A1 and A3 and
PIC16F627A/628A silicon revision A3, A4, A5
and A6.
Unexpected program execution may occur during
data EEPROM write cycles.
Work around
Execute a SLEEP instruction immediately after
setting the EECON1 WR bit and allow the EEIF to
wake the processor from Sleep. This requires the
PEIE bit of the INTCON register and the EEIE bit
of the PIE1 register to be set. All other interrupt
enables must be cleared so that only the EE write
completion will wake the processor.
PIR1, EEIF
1 << PEIE
INTCON
1 << EEIE
PIE1
EECON1, WREN ;enable EE write
0x55
EECON2
0xAA
EECON2
EECON1, WR
EECON1,WREN
This problem is corrected in PIC16F648A
Rev. A5 and PIC16F627A/628A Rev. A8.
Most
during Sleep. Other precautions may be
necessary
operations are complete or in a safe halted
mode before beginning an EEPROM
write.
peripherals
DATA EEPROM WRITE CODE
EXAMPLE
to
;select Bank0
;ensure write complete
;flag is clear
;change to Bank1
;enable only
;peripheral interrupt
;
;enable only EE write
;complete interrupt
;
;required write
;protect squence
;
;second part of
;sequence
;
;initiate write
;suspend operation
;during write
;disable EE write
;program execution
;resumes with this
;instruction upon EE
;write completion
ensure
suspend
all
peripheral
operation
2.
The EEIF flag may be cleared inadvertently
when performing operations on the PIR1 regis-
ter simultaneously with the completion of an
EEPROM write. This condition occurs when the
EEPROM write timer completes at the same
moment that the PIR1 register operation is exe-
cuted. Register operations are those that have
the PIR1 register as the destination and include,
but are not limited to, BSF, BCF, ANDWF,
IORWF and XORWF.
Work around
• Avoid operations on the PIR1 register when
• Poll the WR bit (EECON1<1>) to determine
• Use a timer interrupt to catch any instances
• If periodic interrupts are occurring in addition to
writing to the EEPROM memory.
when the write is complete.
when the EEIF flag is inadvertently cleared.
The timer interrupt should be set longer than
8 ms. If EEIF fails, then the timer interrupt
occurs as a default time out. The WR and
WRERR flags are checked as part of the timer
Interrupt Service Routine to verify the EEPROM
write success.
the EEIF interrupts, then use a secondary flag
to sense write completion. The secondary flag
is set whenever EEPROM writes are active. An
EEPROM write completion is indicated when
the secondary flag is set and the WR flag is
clear.
© 2008 Microchip Technology Inc.