ATTINY84-20MU Atmel, ATTINY84-20MU Datasheet - Page 104

• Manufacturer Part Number: ATTINY84-20MU
• Description: IC MCU AVR 8K FLASH 20MHZ 20-QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY84-20MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 12
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-MLF®, QFN
• Cpu Family: ATtiny
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 20MHz
• Interface Type: SPI/USI
• Total Internal Ram Size: 512Byte
• # I/os (max): 12
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Package Type: MLF
• Processor Series: ATTINY8x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Package: 20MLF
• Family Name: ATtiny
• Maximum Speed: 20 MHz
• For Use With: ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

104
ATtiny24/44/84
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 12-12 on page 104
using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM.
The timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 flag at
BOTTOM.
Figure 12-12. Timer/Counter Timing Diagram, no Prescaling
Figure 12-13 on page 105
(PC and PFC PWM)
OCRnx
TCNTn
OCFnx
(clk
and ICFn
(CTC and FPWM)
clk
(Update at TOP)
clk
TOVn
I/O
I/O
Tn
OCRnx
TCNTn
TCNTn
(clk
as TOP)
/8)
clk
clk
I/O
(FPWM)
I/O
Tn
/1)
(if used
OCRnx - 1
TOP - 1
TOP - 1
shows the same timing data, but with the prescaler enabled.
shows the count sequence close to TOP in various modes. When
Old OCRnx Value
OCRnx
OCRnx Value
TOP
TOP
OCRnx + 1
BOTTOM
TOP - 1
New OCRnx Value
BOTTOM + 1
OCRnx + 2
clk_I/O
8006K–AVR–10/10
TOP - 2
/8)