PIC16F887-I/ML Microchip Technology, PIC16F887-I/ML Datasheet
PIC16F887-I/ML
Specifications of PIC16F887-I/ML
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PIC16F887-I/ML Summary of contents
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... TABLE 1: SILICON DEVREV VALUES Part Number PIC16F882 PIC16F883 PIC16F884 PIC16F886 PIC16F887 Note 1: The device and revision data is stored in the Device ID located at 2006h in program memory. 2: Refer to the “PIC16F88X Memory Programming Specification” (DS41287) for detailed information. © 2009 Microchip Technology Inc. PIC16F88X ...
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... Disruption of the HFINTOSC Write collision on loading R/W bit on ACK Clock-stretching handling Multi-byte transmission Overflow may take additional count Oscillator may stop running at low temps. Spurious Reset Disabling the module generates a clock pulse. (1) Affected Revisions (1) Affected Revisions © 2009 Microchip Technology Inc. ...
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... TABLE 4: SILICON ISSUE SUMMARY (PIC16F886/PIC16F887) Item Module Feature Number LVP Programming 1. MSSP SPI Master 2. ADC VP6 Reference 3. MSSP SPI Master 4. 2 MSSP I C™ Slave 5. 2 MSSP I C™ Master 6. MSSP SPI Slave 7. Timer1 Ext. Crystal 8. Timer1 Ext. Crystal 9. Timer0 Prescaler 10 ...
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... BCF T2CON, TMR2ON CLRF TMR2 MOVWF SSPBUF BSF T2CON, TMR2ON Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X © 2009 Microchip Technology Inc bit ;Data received? ;(Xmit complete?) ; SSPBUF ;Save in user RAM ;W = TXDATA ;Timer2 off ;Clear Timer2 ;Xmit New data ...
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... SSPBUF. If the WCOL is set, clear the bit in software and rewrite the SSPBUF register. Date Codes that pertain to this issue: All engineering and production devices. Affected Silicon Revisions REF PIC16F882 A0 X PIC16F883/PIC16F884 A0 X REF PIC16F886/PIC16F887 A2 X PIC16F88X /64 or OSC DS80302F-page 5 ...
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... CKP bit to release the clock stretching. When the master responds to received data with a NACK the CKP bit properly remains set, and there is no clock stretching. Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X DS80302F-page 6 © 2009 Microchip Technology Inc. ...
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... SDA SCL Master Slave BRG Period © 2009 Microchip Technology Inc. Figure 1 illustrates an expected I in which the SCL line is completely controlled by the master device and the slave device does not attempt to stretch the clock period. Figure 2 illustrates the expected operation of an ...
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... BRG register. However, the behavior of slower slave devices must be understood and speed adjustments made such that no slave performs clock stretching. Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X DS80302F-page 8 BRG Period BRG Period BRG Period BRG Period adjust the BRG Period ...
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... Then restore the SSPM0 bit to the configuration for SPI slave with SS pin enabled. The module is then ready for reception of the following byte. BSF SSPCON, SSPM0 BCF SSPCON, SSPM0 Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X © 2009 Microchip Technology Inc. PIC16F88X DS80302F-page 9 ...
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... Critical Timing of code sequence for instructions following last write to TMR1L or TMR1H. Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X DS80302F-page 10 Due to the time from Timer1 overflow to the reload being application specific, wait for the timer to increment before beginning the reload sequence. This ensures the timer does not miss a rising edge during reload. © ...
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... Modify the TOSE bit in the OPTION register to the opposite configuration for the logic level on the T0CKI pin. 3. Select a prescaler rate other than 1:1 and issue a CLRWDT instruction before switching to the final prescaler rate. Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X PIC16F88X DS80302F-page 11 ...
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... The TRISC3 bit should be set before disabling or enabling the module to tristate the pin, and then cleared before transmission. Affected Silicon Revisions PIC16F882 A0 X PIC16F883/PIC16F884 A0 X PIC16F886/PIC16F887 A2 X DS80302F-page 12 OSC © 2009 Microchip Technology Inc. ...
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... C IC HOLD Ω ( – = 10pF 1.37 µs Therefore 2µs + 1.37µs + ACQ = 4.67µs © 2009 Microchip Technology Inc. and changes 50°C and external impedance of 10k + Hold Capacitor Charging Time T COFF ) 0.05µs/° ;[1] V CHOLD ;[2] V ⎛ ⎞ 1 ;combining [1] and [2] 1 – ...
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... WDT Prescaler Assignment Spurious Reset. Rev. F Document (8/2009) Added Module 11: MSSP (SPI Master Mode); Updated Tables Data Sheet Clarification: Removed Modules and 5 as the Data Sheet has already been updated according to this version of the errata. Added Module 2: ADC. DS80302F-page Module 8: © 2009 Microchip Technology Inc. ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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