PIC16F887-I/ML Microchip Technology, PIC16F887-I/ML Datasheet - Page 10

• Manufacturer Part Number: PIC16F887-I/ML
• Description: IC PIC MCU FLASH 8KX14 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F887-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 44-QFN
• Mfg Application Notes: Intro to Capacitive Sensing Appl Notes Layout and Physical Design Appl Note
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 35
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP/EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 53273-916
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 14-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44QFN2 - SOCKET TRAN ICE 44QFN/40DIPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN444-1001 - DEMO BOARD FOR PICMICRO MCU
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16F88X
3.0
Two methods are available to enter Program/Verify
mode. The “V
and ICSPCLK low while raising MCLR pin from V
V
method can be used for any Configuration Word
selection and must be used if the INTOSC and internal
MCLR options are selected (FOSC<2:0> = 100 or 101
and MCLRE = 0). The V
device from executing code prior to entering Program/
Verify mode. See the timing diagram in Figure 3-1.
The second entry method, “V
applying V
then raising MCLR pin from V
followed by data. This technique is useful when
programming the device when V
for it is not necessary to disconnect V
Program/Verify mode. See the timing diagram in
Figure 3-2.
Once in this mode, the program memory, data memory,
and configuration memory can be accessed and
programmed in serial fashion. ICSPDAT and ICSPCLK
are Schmitt Trigger inputs in this mode. RB6 is tri-state,
regardless of fuse setting.
The sequence that enters the device into the
Programming/Verify mode places all other logic into the
Reset state (the MCLR pin was initially at V
Therefore, all I/O’s are in the Reset state (high-
impedance inputs) and the Program Counter (PC) is
cleared.
When powering down V
undershoot V
applied, damage could be done to the device. To pre-
vent possible damage to the device, power-down V
either before V
When programming a device with the internal MCLR
and INTOSC, care must be taken to prevent code
execution during power-down. If V
before V
to cause device damage. If V
before V
V
slightly after V
Figure 3-3 for the timing.
DS41287D-page 10
IHH
DD
is powered down at the same time as V
(high voltage), then applying V
DD
PP
PROGRAM/VERIFY MODE
DD
, there is a possibility for a V
, there is the possibility of code execution. If
, holding ICSPDAT and ICSPCLK low,
SS
PP
DD
PP
. If V
-first” is entered by holding ICSPDAT
, code execution is prevented. See
or at the same time as V
DD
undershoots V
DD
PP
, make sure V
-first entry prevents the
IL
DD
to V
PP
DD
-first”, is entered by
DD
is already applied,
is powered down
IHH
DD
is powered down
SS
DD
and data. This
(high voltage),
DD
DD
while V
DD
undershoot
PP
.
does not
to enter
or just
PP
IL
IL
PP
to
is
).
FIGURE 3-1:
FIGURE 3-2:
FIGURE 3-3:
ICSPCLK
ICSPCLK
ICSPCLK
ICSPDAT
ICSPDAT
ICSPDAT
Note:
V
V
V
V
V
V
DD
DD
PP
PP
PP
DD
This method of entry is valid, regardless
of Configuration Word selected.
T
T
PPDP
HLD
V
VERIFY MODE ENTRY
V
VERIFY MODE ENTRY
PROGRAM/VERIFY MODE
EXIT
T
 2009 Microchip Technology Inc.
PP
DD
0
HLD
-FIRST PROGRAM/
-FIRST PROGRAM/
0
T
T
HLD
PPDP
0