ATMEGA8535-16JU Atmel, ATMEGA8535-16JU Datasheet - Page 109
![MCU AVR 8K ISP FLASH MEM 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535-16JU
Manufacturer Part Number
ATMEGA8535-16JU
Description
MCU AVR 8K ISP FLASH MEM 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16JU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
512Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8535-16JU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 109 of 321
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2502K–AVR–10/06
Figure 50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
Figure 51 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode, the OCR1x Register is updated at BOTTOM. The
timing diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by
BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag
at BOTTOM.
Figure 51. Timer/Counter Timing Diagram, no Prescaling
Figure 52 shows the same timing data, but with the prescaler enabled.
TCNTn
OCRnx
OCFnx
(clk
clk
(PC and PFC PWM)
clk
and ICFn
(CTC and FPWM)
TOVn
(Update at TOP)
I/O
I/O
Tn
/8)
TCNTn
TCNTn
OCRnx
as TOP)
(clk
clk
clk
I/O
(FPWM)
I/O
Tn
/1)
(if used
OCRnx - 1
TOP - 1
TOP - 1
Old OCRnx Value
OCRnx
OCRnx Value
TOP
TOP
OCRnx + 1
ATmega8535(L)
BOTTOM
TOP - 1
New OCRnx Value
OCRnx + 2
BOTTOM + 1
TOP - 2
clk_I/O
109
/8)
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