ATMEGA8535-16JU Atmel, ATMEGA8535-16JU Datasheet - Page 129
![MCU AVR 8K ISP FLASH MEM 44-PLCC](/photos/6/70/67043/453-44-plcc_sml.jpg)
ATMEGA8535-16JU
Manufacturer Part Number
ATMEGA8535-16JU
Description
MCU AVR 8K ISP FLASH MEM 44-PLCC
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA8535-16JU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, TWI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
16MHz
Total Internal Ram Size
512Byte
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PLCC
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA8535-16JU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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- Download datasheet (3Mb)
2502K–AVR–10/06
Table 51. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the
COM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/O
pin it is connected to. However, note that the Data Direction Register (DDR) bit corre-
sponding to OC2 pin must be set in order to enable the output driver.
When OC2 is connected to the pin, the function of the COM21:0 bits depends on the
WGM21:0 bit setting. Table 52 shows the COM21:0 bit functionality when the WGM21:0
bits are set to a Normal or CTC mode (non-PWM).
Table 52. Compare Output Mode, non-PWM Mode
Table 53 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fast
PWM mode.
Table 53. Compare Output Mode, Fast PWM Mode
Note:
Mode
COM21
0
1
2
3
COM21
0
0
1
1
0
0
1
1
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 def-
1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the
WGM21
(CTC2)
COM20
initions. However, the functionality and location of these bits are compatible with
previous versions of the timer.
Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 123 for more details.
0
0
1
1
0
1
0
1
COM20
WGM20
(PWM2)
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Reserved
Clear OC2 on Compare Match, set OC2 at TOP (Non-Inverting).
Set OC2 on Compare Match, clear OC2 at TOP (Inverting).
0
1
0
1
Description
Normal port operation, OC2 disconnected.
Toggle OC2 on Compare Match.
Clear OC2 on Compare Match.
Set OC2 on Compare Match.
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
(1)
(1)
TOP
0xFF
0xFF
OCR2
0xFF
ATmega8535(L)
Update of
OCR2
Immediate
TOP
Immediate
BOTTOM
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
129
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