DSPIC30F3012-20I/SO Microchip Technology, DSPIC30F3012-20I/SO Datasheet - Page 2

• Manufacturer Part Number: DSPIC30F3012-20I/SO
• Description: IC DSPIC MCU/DSP 24K 18SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F3012-20I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 24KB (8K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 24KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC30F005 - MODULE SCKT DSPIC30F 18DIP/SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F301220ISO

dsPIC30F3012/3013
TABLE 2:
DS80448D-page 2
Operations
Operations
Note 1:
Controller
Compare
Compare
Interrupt
Module
Output
Output
Sleep
Mode
Timer
I
CPU
CPU
CPU
CPU
ADC
PSV
PSV
2
PLL
PLL
I
I/O
C™
2
C
Only those issues indicated in the last column apply to the current silicon revision.
Modification
Sleep Mode
Slave Mode
Sleep Mode
PWM Mode
Lock Status
Instructions
Multiplexed
Addressing
Instruction
Nested DO
Instruction
MAC Class
Address
Feature
Port Pin
with IC1
SILICON ISSUE SUMMARY
with ±4
DAW.b
Loops
10-bit
DISI
bit
—
—
—
—
—
—
Number
Item
12.
10.
11.
13.
14.
15.
16.
17.
1.
2.
3.
4.
5.
6.
7.
8.
9.
Sequential MAC instructions, which prefetch data from Y data
space using ±4 address modification will cause an address error
trap.
The Decimal Adjust instruction, DAW.b, may improperly clear the
Carry bit, C (SR<0>).
In certain instructions, fetching one of the operands from
program memory using Program Space Visibility (PSV) will
corrupt specific bits in the STATUS Register, SR.
When using two DO loops in a nested fashion, terminating the
inner-level DO loop by setting the EDT bit (CORCON<11>) will
produce unexpected results.
An interrupt occurring immediately after modifying the CPU IPL,
interrupt IPL, interrupt enable, or interrupt flag may cause an
address error trap.
The DISI instruction will not disable interrupts if a DISI
instruction is executed in the same instruction cycle that the
DISI counter decrements to zero.
Output compare will produce a glitch when loading 0% duty
cycle in PWM mode. It will also miss the next compare after the
glitch.
The output compare module will produce a glitch on the output
when an I/O pin is initially set high and the module is configured
to drive the pin low at a specified time.
ADC event triggers from the INT0 pin will not wake-up the device
from Sleep mode if the SMPI bits are non-zero.
If 4x or 8x PLL mode is used, the input frequency range is 5 MHz-
10 MHz instead of 4 MHz-10 MHz.
Execution of the Sleep instruction (PWRSAV #0) may cause
incorrect program operation after the device wakes up from
Sleep. The current consumption during Sleep may also increase
beyond the specifications listed in the device data sheet.
The I
I
The Port I/O pin multiplexed with the Input Capture 1 (IC1)
function cannot be used as a digital input pin when the UART
auto-baud feature is enabled.
When the I
the same address bits (A10 and A9) as other I
A10 and A9 bits may not work as expected.
Clock switching prevents the device from waking up from Sleep.
The PLL LOCK Status bit (OSCCON<5>) can occasionally get
cleared and generate an oscillator failure trap even when the
PLL is still locked and functioning correctly.
An address error trap occurs in certain addressing modes when
accessing the first four bytes of any PSV page.
2
C slave.
2
C module loses incoming data bytes when operating as an
2
C module is configured for 10-bit addressing using
Issue Summary
2
C devices, the
© 2010 Microchip Technology Inc.
Revisions
B0
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)