DSPIC30F1010-30I/SO Microchip Technology, DSPIC30F1010-30I/SO Datasheet - Page 22

• Manufacturer Part Number: DSPIC30F1010-30I/SO
• Description: IC DSPIC MCU/DSP 6K 28SOIC
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F1010-30I/SO

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 6KB (2K x 24)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SOIC (7.5mm Width)
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240002, DM300023, DM330011
• Package: 28SOIC W
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Number Of Programmable I/os: 21
• Interface Type: I2C/SPI/UART
• On-chip Adc: 6-chx10-bit
• Number Of Timers: 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
49. Module: Analog Comparator
50. Module: ADC
DS80445D-page 22
Output from the Analog Comparator may falsely
switch state if an ADC conversion trigger and
two or more PWM edges occur at the same
time. This behavior is observed when multiple
PWM outputs are used in the Independent Time
Base mode and the Analog Comparator is con-
figured as a Fault or as a current-limit input to
the PWM.
As a result of this erratum, the PWM module
may exhibit spurious faults or current-limit
events.
Work around
Ensure that the ADC conversion is triggered
when multiple PWM edges are not aligned.
Affected Silicon Revisions
If the ADC module is in an enabled state when the
device enters Sleep mode as a result of executing
a PWRSAV #0 instruction, the device power-down
current (I
in the device data sheet. This may happen even if
the ADC module is disabled by clearing the ADON
bit prior to entering Sleep mode.
Work around
In order to remain within the I
listed in the device data. sheet, the user software
must completely disable the ADC module by
setting the ADC Module Disable bit in the
corresponding Peripheral Module Disable register
(PMDx), prior to executing a PWRSAV
instruction.
Affected Silicon Revisions
A1
A1
X
X
A2
A2
X
X
PD
) may exceed the specifications listed
A3
A3
X
X
PD
specifications
#0
© 2010 Microchip Technology Inc.