PIC18F2525-I/SO Microchip Technology, PIC18F2525-I/SO Datasheet - Page 9

• Manufacturer Part Number: PIC18F2525-I/SO
• Description: IC MCU FLASH 24KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2525-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 48KB (24K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3986 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 4.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163022, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3DB18F4620 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For PIC18F2221/4221 devices, the code memory
space extends from 0000h to 00FFFh (4 Kbytes) in one
4-Kbyte block. For PIC18F2321/4321 devices, the
code memory space extends from 0000h to 01FFFh
(8 Kbytes) in two 4-Kbyte blocks. Addresses, 0000h
through 07FFh, however, define a variable “Boot Block”
region that is treated separately from Block 0. All of
these blocks define code protection boundaries within
the code memory space.
The size of the Boot Block in PIC18F2221/2321/4221/
4321 devices can be configured as 256, 512 or
1024 words (see
BBSIZ<1:0>
FIGURE 2-8:
 2010 Microchip Technology Inc.
Note:
3FFFFFh
01FFFFh
000000h
200000h
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register.
Unimplemented
Code Memory
Configuration
Read as ‘0’
bits
and ID
Space
Figure
in
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2221/2321/4221/4321 DEVICES
2-8). This is done through the
the
Configuration
Boot Block*
1K word
1K word
Block 0
11/10
register,
PIC18F2XXX/4XXX FAMILY
Unimplemented
(PIC18FX321)
Reads all ‘0’s
Boot Block*
1.5K words
512 words
2K words
8 Kbytes
Block 1
Block 0
01
MEMORY SIZE/DEVICE
CONFIG4L (see
increasing the size of the Boot Block decreases the
size of Block 0.
TABLE 2-7:
BBSIZ<1:0>
1.75K words
Boot Block*
256 words
Block 0
PIC18F2221
PIC18F4221
PIC18F2321
PIC18F4321
00
Device
Figure
Boot Block*
11/10/01
0.5K words
512 words
IMPLEMENTATION OF CODE
MEMORY
Block 0
Unimplemented
(PIC18FX221)
Reads all ‘0’s
2-8). It is important to note that
Code Memory Size (Bytes)
4 Kbytes
1K word
Block 1
000000h-000FFFh (4K)
000000h-001FFFh (8K)
0.75K words
Boot Block*
256 words
Block 0
00
DS39622L-page 9
000000h
0001FFh
000200h
0003FFh
000400h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
1FFFFFh
Address
Range