PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 271
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6527-I/PT
Manufacturer Part Number
PIC18F6527-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F8627T-IPT.pdf
(44 pages)
4.PIC18F6527-IPT.pdf
(10 pages)
5.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F6527-I/PT
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
NOVACAP
Quantity:
20 000
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
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Quantity:
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Part Number:
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MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- PIC18F8627T-IPT PDF datasheet #3
- PIC18F6527-IPT PDF datasheet #4
- PIC18F8622-IPT PDF datasheet #5
- Current page: 271 of 446
- Download datasheet (7Mb)
20.4.2
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSRx register will transfer the data to
the RCREGx register; if the RCxIE enable bit is set, the
interrupt generated will wake the chip from the low-
power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
TABLE 20-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
© 2008 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISG
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.
Name
EUSART SYNCHRONOUS SLAVE
RECEPTION
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register High Byte
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
TRISC7
PSPIF
PSPIE
PSPIP
SPEN
CSRC
Bit 7
—
TRISC6
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
—
TRISC5
RC1IF
RC1IE
RC1IP
SREN
TXEN
Bit 5
—
—
TRISC4
TRISG4
INT0IE
TX1IE
TX1IP
CREN
SYNC
TX1IF
SCKP
Bit 4
TRISC3
TRISG3
SSP1IF
SSP1IE
SSP1IP
ADDEN
SENDB
BRG16
To set up a Synchronous Slave Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
RBIE
Bit 3
PIC18F8722 FAMILY
Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
If interrupts are desired, set enable bit, RCxIE.
If 9-bit reception is desired, set bit, RX9.
To enable reception, set enable bit, CREN.
Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREGx register.
If any error occurred, clear the error by clearing
bit, CREN.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR0IF
CCP1IF
CCP1IE
CCP1IP
TRISC2
TRISG2
BRGH
FERR
Bit 2
—
TMR2IE
TMR2IP
TMR2IF
TRISC1
TRISG1
INT0IF
OERR
TRMT
WUE
Bit 1
TMR1IE
TMR1IP
TMR1IF
TRISC0
TRISG0
ABDEN
RX9D
TX9D
DS39646C-page 269
RBIF
Bit 0
on page
Values
Reset
57
60
60
60
60
60
59
59
59
61
61
59
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