PIC18F6527-I/PT Microchip Technology, PIC18F6527-I/PT Datasheet - Page 70
![IC PIC MCU FLASH 24KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6527-I/PT
Manufacturer Part Number
PIC18F6527-I/PT
Description
IC PIC MCU FLASH 24KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.DV164136.pdf
(446 pages)
3.PIC18F8627T-IPT.pdf
(44 pages)
4.PIC18F6527-IPT.pdf
(10 pages)
5.PIC18F8622-IPT.pdf
(448 pages)
Specifications of PIC18F6527-I/PT
Program Memory Type
FLASH
Program Memory Size
48KB (24K x 16)
Package / Case
64-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
54
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12-ch x 10-bit
Package
64TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Manufacturer:
NOVACAP
Quantity:
20 000
Company:
Part Number:
PIC18F6527-I/PT
Manufacturer:
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Quantity:
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Quantity:
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Part Number:
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Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- DV164136 PDF datasheet #2
- PIC18F8627T-IPT PDF datasheet #3
- PIC18F6527-IPT PDF datasheet #4
- PIC18F8622-IPT PDF datasheet #5
- Current page: 70 of 446
- Download datasheet (7Mb)
PIC18F8722 FAMILY
5.1.3.4
Device Resets on stack overflow and stack underflow
conditions are enabled by setting the STVREN bit in
Configuration Register 4L. When STVREN is set, a full
or underflow will set the appropriate STKFUL or
STKUNF bit and then cause a device Reset. When
STVREN is cleared, a full or underflow condition will set
the appropriate STKFUL or STKUNF bit, but not cause
a device Reset. The STKFUL or STKUNF bits are
cleared by the user software or a Power-on Reset.
5.1.4
A fast register stack is provided for the STATUS,
WREG and BSR registers, to provide a “fast return”
option for interrupts. The stack for each register is only
one level deep and is neither readable nor writable. It is
loaded with the current value of the corresponding reg-
ister when the processor vectors for an interrupt. All
interrupt sources will push values into the Stack regis-
ters. The values in the registers are then loaded back
into their associated registers if the RETFIE, FAST
instruction is used to return from the interrupt.
If both low and high-priority interrupts are enabled, the
stack registers cannot be used reliably to return from
low-priority interrupts. If a high-priority interrupt occurs
while servicing a low-priority interrupt, the Stack regis-
ter values stored by the low-priority interrupt will be
overwritten. In these cases, users must save the key
registers in software during a low-priority interrupt.
If interrupt priority is not used, all interrupts may use the
fast register stack for returns from interrupt. If no inter-
rupts are used, the fast register stack can be used to
restore the STATUS, WREG and BSR registers at the
end of a subroutine call. To use the fast register stack
for a subroutine call, a CALL label, FAST instruction
must be executed to save the STATUS, WREG and
BSR
RETURN, FAST instruction is then executed to restore
these registers from the fast register stack.
Example 5-1 shows a source code example that uses
the fast register stack during a subroutine call and return.
EXAMPLE 5-2:
DS39646C-page 68
MAIN: ORG
…
TABLE MOVF
registers
MOVLW
CALL
ORG
RLNCF
ADDWF
RETLW
RETLW
RETLW
RETLW
RETLW
END
FAST REGISTER STACK
Stack Full and Underflow Resets
to
0x0000
0x00
TABLE
0x8000
PCL, F
W, W
PCL
‘A’
‘B’
‘C’
‘D’
‘E’
the
COMPUTED GOTO USING AN OFFSET VALUE
fast
register
; A simple read of PCL will update PCLATH, PCLATU
; Multiply by 2 to get correct offset in table
; Add the modified offset to force jump into table
stack.
A
EXAMPLE 5-1:
5.1.5
There may be programming situations that require the
creation of data structures, or look-up tables, in
program memory. For PIC18 devices, look-up tables
can be implemented in two ways:
• Computed GOTO
• Table Reads
5.1.5.1
A computed GOTO is accomplished by adding an offset
to the program counter. An example is shown in
Example 5-2.
A look-up table can be formed with an ADDWF
instruction and a group of RETLW nn instructions. The W
register is loaded with an offset into the table before exe-
cuting a call to that table. The first instruction of the called
routine is the ADDWF PCL instruction. The next instruction
executed will be one of the RETLW nn instructions that
returns the value ‘nn’ to the calling function.
The offset value (in WREG) specifies the number of
bytes that the program counter should advance and
should be multiples of 2 (LSb = 0).
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
CALL SUB1, FAST
SUB1
Note:
RETURN, FAST
•
•
•
•
LOOK-UP TABLES IN PROGRAM
MEMORY
The “ADDWF
update the PCLATH and PCLATU registers.
A read operation on PCL must be performed
to update PCLATH and PCLATU.
Computed GOTO
FAST REGISTER STACK
CODE EXAMPLE
;STATUS, WREG, BSR
;SAVED IN FAST REGISTER
;STACK
;RESTORE VALUES SAVED
;IN FAST REGISTER STACK
© 2008 Microchip Technology Inc.
PCL” instruction does not
PCL
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