PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 40

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-6:
TABLE 4-7:
Legend:
Note
Legend:
Note
BF80_6000 U1MODE
BF80_6010
BF80_6020 U1TXREG
BF80_6030 U1RXREG
BF80_6040 U1BRG
BF80_6200 U2MODE
BF80_5050
BF80_5260
BF80_5200
BF80_5210
BF80_5220
BF80_5230
BF80_5240
BF80_5250
BF80_5260
Virtual
Virtual
Addr
Addr
SFR
SFR
1:
1:
I2C2STAT
U1STA
I2C2CON
I2C2MSK
I2C2BRG
I2C1TRN
I2C1RCV
I2C2ADD
I2C2TRN
I2C2RCV
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Regis-
ters” for more information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET, and INV Registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
Name
Name
SFR
SFR
(1)
(1)
(1)
(1)
I2C1-2 REGISTERS MAP
UART1-2 REGISTERS MAP
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
ACKSTAT
31/15
31/15
Bits
Bits
ON
UTXISEL<1:0>
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
30/14
30/14
Bits
FRZ
FRZ
Bits
FRZ
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXINV
29/13
SIDL
SIDL
29/13
Bits
SIDL
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
(CONTINUED)
SCLREL
URXEN
28/12
IREN
IREN
28/12
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXBRK
RTSMD
RTSMD
STRICT
27/11
27/11
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UTXEN
26/10
26/10
A10M
Bits
Bits
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GCSTAT
DISSLW
UTXBF
25/9
Bits
Bits
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
UEN<1:0>
UEN<1:0>
ADM_EN
ADD10
TRMT
SMEN
Bits
24/8
24/8
TX8
RX8
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BRG<15:0>
IWCOL
WAKE
WAKE
GCEN
Bits
23/7
23/7
Bits
URXISEL<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LPBACK
LPBACK
STREN
I2COV
Bits
22/6
Bits
22/6
I2C2BRG<11:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ABAUD
ADDEN
ABAUD
ACKDT
Bits
21/5
Bits
21/5
D/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ACKEN
RXINV
RXINV
RIDLE
I2CR1DATA<7:0>
I2CR1DATA<7:0>
Transmit Register
I2CT1DATA<7:0>
I2CT1DATA<7:0>
20/4
Receive Register
20/4
Bits
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
ADDR<7:0>
BRGH
PERR
BRGH
RCEN
19/3
Bits
19/3
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
FERR
18/2
Bits
18/2
PEN
R/W
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PDSEL<1:0>
PDSEL<1:0>
RSEN
OERR
17/1
Bits
17/1
Bits
RBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
URXDA
STSEL
STSEL
Bits
16/0
SEN
Bits
16/0
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—