PIC32MX360F512L-80I/PT Microchip Technology, PIC32MX360F512L-80I/PT Datasheet - Page 44

• Manufacturer Part Number: PIC32MX360F512L-80I/PT
• Description: IC PIC MCU FLASH 512K 100-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512L-80I/PT

• Program Memory Type: FLASH
• Program Memory Size: 512KB (512K x 8)
• Package / Case: 100-TFQFP
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC32MX3xx
• Core: MIPS
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C , SPI , UART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 85
• Number Of Timers: 5 x 16 bit
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Controller Family/series: PIC32
• No. Of I/o's: 85
• Ram Memory Size: 32KB
• Cpu Speed: 80MHz
• No. Of Timers: 6
• Embedded Interface Type: EUART, I2C, PSP, SPI
• No. Of Pwm Channels: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1000 - PIC32 BREAKOUT BOARDAC244003 - TEST BD MPLAB REAL ICE LOOPBACKAC244006 - KIT MPLAB REAL ICE TRACEDM320001 - KIT EVAL PIC32 STARTERAC164333 - MODULE SKT FOR PM3 100QFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 4-12:
BF88_30C0 DCH0DSIZ
BF88_30D0 DCH0SPTR
Legend:
Note
BF88_3060 DCH0CON
BF88_3070 DCH0ECON
BF88_3080
BF88_3090 DCH0SSA
BF88_30A0 DCH0DSA
BF88_30B0 DCH0SSIZ
BF88_30E0 DCH0DPTR
BF88_30F0 DCH0CSIZ
BF88_3100 DCH0CPTR
BF88_3110 DCH0DAT
BF88_3120 DCH1CON
BF88_3130 DCH1ECON
BF88_3140
BF88_3150 DCH1SSA
BF88_3160 DCH1DSA
Virtual
Addr
SFR
1:
DCH0INT
DCH1INT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers except DCHxSPTR, DCHxDPTR, and DCHxCPTR have corresponding CLR, SET, and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8, and 0xC, respectively. See Section 12.1.1 “CLR,
SET and INV Registers” for more information.
Name
SFR
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
31/15
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
Bits
—
—
—
CHSIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHSIRQ<7:0>
—
—
27/11
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
25/9
Bits
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHCHNS
CHCHNS
Bits
24/8
CHSSA<31:0>
CHDSA<31:0>
CHSSA<31:0>
CHDSA<31:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CFORCE
CFORCE
CHSDIE
CHSDIF
CHSDIE
CHSDIF
CHEN
CHEN
Bits
23/7
—
—
—
—
—
—
—
—
—
CABORT
CABORT
CHSHIE
CHSHIF
CHSHIE
CHSHIF
CHAED
CHAED
Bits
22/6
—
—
—
—
—
—
—
—
—
CHDDIE
CHDDIE
CHCHN
CHDDIF
CHCHN
CHDDIF
PATEN
PATEN
Bits
21/5
—
—
—
—
—
—
—
—
—
SIRQEN
CHDHIE
SIRQEN
CHDHIE
CHDHIF
CHDHIF
CHAEN
CHAEN
20/4
Bits
CHDPTR<7:0>
CHCPTR<7:0>
CHPDAT<7:0>
—
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
CHAIRQ<7:0>
CHSSIZ<7:0>
CHDSIZ<7:0>
CHCSIZ<7:0>
CHSTR<7:0>
AIRQEN
CHBCIE
AIRQEN
CHBCIE
CHBCIF
CHBCIF
19/3
Bits
—
—
—
—
—
—
—
—
—
—
—
CHEDET
CHEDET
CHCCIE
CHCCIF
CHCCIE
CHCCIF
18/2
Bits
—
—
—
—
—
—
—
—
—
—
—
CHTAIE
CHTAIF
CHTAIE
CHTAIF
Bits
17/1
—
—
—
—
—
—
—
—
—
—
—
(1)
CHPRI<1:0>
CHPRI<1:0>
CHERIE
CHERIF
CHERIE
CHERIF
Bits
16/0
—
—
—
—
—
—
—
—
—
—
—