M30281F6HP#U9B Renesas Electronics America, M30281F6HP#U9B Datasheet - Page 116
M30281F6HP#U9B
Manufacturer Part Number
M30281F6HP#U9B
Description
IC M16C/28 MCU FLASH 48K 64LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30281F6HP#U9B
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30281F6HP#U9BM30281F6HP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30281F6HP#U9BM30281F6HP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
1
Figure 11.5 Transfer Cycles for Source Read
. v
6
J
0
C
2
9
2 /
0 .
B
0
8
0
(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address
(3) When the source read cycle under condition (1) has one wait state inserted
(4) When the source read cycle under condition (2) has one wait state inserted
(2) When the transfer unit is 16 bits and the source address of transfer is an odd address.
0
CPU clock
CPU clock
CPU clock
CPU clock
G
4
WR signal
WR signal
WR signal
WR signal
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
Address
bus
RD signal
Data
bus
J
7
a
o r
NOTES:
0 -
. n
u
2
1. The same timing changes occur with the respective conditions at the destination as at the source.
3
p
0
, 1
0
(
M
2
0
1
0
6
7
C
CPU use
CPU use
CPU use
2 /
CPU use
CPU use
, 8
CPU use
CPU use
CPU use
page 94
M
1
6
C
2 /
f o
8
3
) B
Source
8
Source
5
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
cycle
Dummy
cycle
Destination
Dummy
cycle
Dummy
cycle
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
Dummy
cycle
Dummy
cycle
CPU use
CPU use
11. DMAC
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