M30281F6HP#U9B Renesas Electronics America, M30281F6HP#U9B Datasheet - Page 392
M30281F6HP#U9B
Manufacturer Part Number
M30281F6HP#U9B
Description
IC M16C/28 MCU FLASH 48K 64LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/28r
Datasheet
1.M30280F6HPU9.pdf
(425 pages)
Specifications of M30281F6HP#U9B
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, POR, PWM, Voltage Detect, WDT
Number Of I /o
55
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
64-LQFP
For Use With
R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30281F6HP#U9BM30281F6HP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30281F6HP#U9BM30281F6HP#U3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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8. If the CPU reads the AD register i (i = 0 to 7) at the same time the conversion result is stored in the AD
9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0 register
10. When setting the ADST bit in the ADCON register to "0" to stop A/D conversion during A/D converting
0 .
B
0
0
register i after completion of A/D conversion, an incorrect value may be stored in the AD register i. This
problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for CPU
clock.
to “0” (A/D conversion halted), the conversion result of the A/D converter is indeterminate. The contents
of AD register i irrelevant to A/D conversion may also become indeterminate. If while A/D conversion is
underway the ADST bit is cleared to “0” in a program, ignore the values of all AD register i.
operation in single sweep conversion mode, A/D delayed trigger mode 0, or A/D delayed trigger mode 1,
set the ADST bit to "0" after an interrupt is disabled because the A/D interrupt request may be generated.
8
0
• When operating in one-shot, single-sweep mode, simultaneous sample sweep mode, delayed
• When operating in repeat mode or repeat sweep mode 0 or 1
G
4
J
Check to see that A/D conversion is completed before reading the target AD register i. (Check the IR
bit in the ADIC register to see if A/D conversion is completed.)
Use the main clock for CPU clock directly without dividing it.
7
trigger mode 0 or delayed trigger mode 1
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3
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page 370
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20. Precautions
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