MCIMX515CJM6C Freescale Semiconductor, MCIMX515CJM6C Datasheet - Page 120

• Manufacturer Part Number: MCIMX515CJM6C
• Description: MULTIMEDIA PROC 529-LFBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX51r

Specifications of MCIMX515CJM6C

• Core Processor: ARM Cortex-A8
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: 1-Wire, EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 128
• Program Memory Type: ROMless
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.8 V ~ 1.15 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 529-LFBGA
• Processor Series: i.MX51
• Core: ARM Cortex A8
• Data Bus Width: 32 bit
• Program Memory Size: 36 KB
• Data Ram Size: 128 KB
• Interface Type: I2C, SPI, SSI, UART, USB
• Maximum Clock Frequency: 200 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 0.8 V to 1.15 V
• Maximum Operating Temperature: + 95 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: MCIMX51EVKJ
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Electrical Characteristics
4.7.11.2
Figure 77
host terminates transfer,
Table 95
120
Parameter
ATA
tn, tj
—
lists the timing parameters for UDMA in burst.
shows timing when the UDMA in transfer starts,
Ultra DMA (UDMA) Input Timing
Parameter
Figure
Figure 76
from
tkjn
ton
toff
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 4
75,
Table 94. MDMA Read and Write Timing Parameters (continued)
Figure 78. UDMA In Host Terminates Transfer Timing Diagram
Figure 79
tn= tj= tkjn = (max(time_k,. time_jn)
ton = time_on
toff = time_off
Figure 77. UDMA In Transfer Starts Timing Diagram
shows timing when the UDMA in device terminates transfer, and
×
×
T – tskew1
T – tskew1
×
Value
T – (tskew1 + tskew2 + tskew6)
Figure 78
shows timing when the UDMA in
Freescale Semiconductor
Controlling
Variable
time_jn
—