PIC16F1946-E/PT Microchip Technology, PIC16F1946-E/PT Datasheet
PIC16F1946-E/PT
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... LCD Driver and nanoWatt XLP Technology 2010 Microchip Technology Inc. PIC16F/LF1946/47 Data Sheet 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary DS41414A ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Programmable Code Protection • High Endurance Flash/EEPROM cell: - 100,000 write Flash endurance - 1,000,000 write EEPROM endurance - Flash/Data EEPROM retention: > 40 years • Wide Operating Voltage Range: - 1.8V-5.5V (PIC16F1946/47) - 1.8V-3.6V (PIC16LF1946/47) 2010 Microchip Technology Inc. PIC16F/LF1946/47 PIC16LF1946/47 Low-Power Features: • Standby Current 1.8V, typical • ...
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... Power mode control - Software enable hysteresis • Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection PIC16F/LF1946/47 Family Types PIC16F1946 8192 256 512 PIC16LF1946 PIC16F1947 16384 256 ...
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... SEG25/SS1/C1IN3-/C2IN3-/C3IN3-/CPS5/AN5/RF7 SEG24/C1IN+/CPS11/AN11/RF6 SEG23/DACOUT/C1IN1-/C2IN1-/CPS10/AN10/RF5 SEG22/C2IN+/CPS9/AN9/RF4 SEG21/C1IN2-/C2IN2-/C3IN2-/CPS8/AN8/RF3 SEG20/SRQ/C1OUT/CPS7/AN7/RF2 Note 1: Pin location selected by APFCON register setting. 2: QFN package orientation is the same. No leads are present on the QFN package. 2010 Microchip Technology Inc. PIC16F/LF1946/47 PIC16F/LF1946/47 ...
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... SEG1 — — — — SEG2 — — — — SEG3 — — — SDO2 SEG4 — — — SDI2 SEG5 — — — SDA2 SCK2/ SEG6 — — — SCL2 SS2 SEG7 — — — 2010 Microchip Technology Inc. ...
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... SS Note 1: Pin functions can be moved using the APFCON register(s). 2: Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. 3: See Section 8.0. 2010 Microchip Technology Inc. PIC16F/LF1946/47 (1) — — — P2D — (1) — — ...
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... Appendix A: Data Sheet Revision History.......................................................................................................................................... 425 Appendix B: Migrating From Other PIC® Devices ............................................................................................................................. 425 Index .................................................................................................................................................................................................. 427 The Microchip Web Site ..................................................................................................................................................................... 435 Customer Change Notification Service .............................................................................................................................................. 435 Customer Support .............................................................................................................................................................................. 435 Reader Response .............................................................................................................................................................................. 436 Product Identification System............................................................................................................................................................. 437 DS41414A-page 6 Preliminary 2010 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 7 ...
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... PIC16F/LF1946/47 NOTES: DS41414A-page 8 Preliminary 2010 Microchip Technology Inc. ...
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... ECCP3 CCP4 CCP5 Comparators EUSARTS EUSART1 EUSART2 Master Synchronous Serial Ports MSSP1 MSSP2 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2010 Microchip Technology Inc. PIC16F/LF1946/47 of the ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... ECCP2 Note 1: See applicable chapters for more information on peripherals. DS41414A-page 10 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 Timer4 Timer6 MSSPx ECCP3 CCP4 CCP5 Preliminary RAM EEPROM PORTA PORTB PORTC PORTD PORTE PORTF PORTG Comparators EUSARTx 2010 Microchip Technology Inc. ...
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... SEG8 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin function is selectable via the APFCON register. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type TTL CMOS General purpose I/O. ...
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... LCD Analog output. ST CMOS General purpose I/O. ST — SPI data input C™ data input/output. — AN LCD Analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... VLCD1 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin function is selectable via the APFCON register. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type ST CMOS General purpose I/O. — ...
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... A/D Channel 7 input. AN — Capacitive sensing input 7. — CMOS Comparator C1 output. — CMOS SR Latch non-inverting output. — AN LCD Analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... SEG43 Legend Analog input or output CMOS = CMOS compatible input or output TTL = TTL compatible input High Voltage XTAL = Crystal Note 1: Pin function is selectable via the APFCON register. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Input Output Type Type TTL CMOS General purpose I/O. ...
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... General purpose input. ST — Master Clear with internal pull-up. HV — Programming voltage. Power — Positive supply. Power — Ground reference. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2010 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 28.0 “Instruction Set Summary” for more details. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 17 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W Reg Timer Brown-out Reset Preliminary RAM Addr 12 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2010 Microchip Technology Inc. ...
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... Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device PIC16F/LF1946 PIC16F/LF1947 2010 Microchip Technology Inc. PIC16F/LF1946/47 The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3 ...
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... PIC16F/LF1947 PC<14:0> 15 Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 1FFFh Page 4 2000h Page 7 3FFFh 4000h Rollover to Page 0 Rollover to Page 7 7FFFh 2010 Microchip Technology Inc. ...
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... The BRW instruction makes this type of table very sim- ple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 21 ...
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... STATUS • FSR0 Low • FSR0 High • FSR1 Low • FSR1 High • BSR • WREG • PCLATH • INTCON Note: The core registers are the first 12 addresses of every data memory bank. “Indirect Preliminary 2010 Microchip Technology Inc. ...
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... For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. PIC16F/LF1946/47 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: MEMORY MAP TABLES Device Banks PIC16F/LF1946/47 0-7 8-15 16-23 23-31 Preliminary 2010 Microchip Technology Inc. Table No. Table 3-3 Table 3-4, Table 3-7 Table 3-5 Table 3-6, Table 3-8 ...
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... Bytes 070h 0F0h 170h Accesses 70h – 7Fh 07Fh 0FFh 17Fh Legend: = Unimplemented data memory locations, read as ‘0’. Note 1: Not available on PIC16F1946. BANK 2 BANK 3 BANK 4 INDF0 180h INDF0 200h INDF0 INDF1 181h INDF1 201h INDF1 PCL 182h ...
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... Accesses Accesses 70h – 7Fh 70h – 7Fh 4FFh 57Fh 47Fh Legend: = Unimplemented data memory locations, read as ‘0’ Note 1: Not available on PIC16F1946. BANK 10 BANK 11 BANK 12 INDF0 INDF0 INDF0 580h 600h INDF1 INDF1 INDF1 581h 601h PCL ...
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TABLE 3-5: PIC16F/LF1946/47 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
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TABLE 3-6: PIC16F/LF1946/47 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... Unimplemented Read as ‘0’ 7EFh Legend: = Unimplemented data memory locations, read as ‘0’. 2010 Microchip Technology Inc. PIC16F/LF1946/47 TABLE 3-8: PIC16F/LF1946/47 MEMORY MAP, BANK 31 Bank 31 F8Ch ICDIO F8Dh ICDCON0 F8Eh ICDCON1 F8Fh ICDCON2 — ...
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... PIC16F/LF1946/47 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device Bank( PIC16F/LF1946/ 9-14 15 16-30 31 DS41414A-page 30 Page No Preliminary 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... SCS<1:0> 0011 1-00 0011 1-00 LFIOFR HFIOFS 00q0 0q0- qqqq qq0- xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu GO/DONE ADON -000 0000 -000 0000 ADPREF1 ADPREF0 0000 -000 0000 -000 — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... STR1B STR1A ---0 0001 ---0 0001 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 PSS2BD<1:0> 0000 0000 0000 0000 STR2B STR2A ---0 0001 ---0 0001 C5TSEL<1:0> ---- --00 ---- --00 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... IOCBP1 IOCBP0 0000 0000 0000 0000 IOCBN1 IOCBN0 0000 0000 0000 0000 IOCBF1 IOCBF0 0000 0000 0000 0000 — — — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... OERR RX9D 0000 000x 0000 000x TRMT TX9D 0000 0010 0000 0010 WUE ABDEN 01-0 0-00 01-0 0-00 — — — — — — — — — — — — — — — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... COM0 COM0 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... INTF IOCIF 0000 000x 0000 000u — — 2010 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2010 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2010 Microchip Technology Inc. PIC16F/LF1946/47 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2010 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2010 Microchip Technology Inc. PIC16F/LF1946/47 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS41414A-page 50 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2010 Microchip Technology Inc. ...
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... FIGURE 3-10: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 2010 Microchip Technology Inc. PIC16F/LF1946/47 Indirect Addressing 0 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary ...
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... FIGURE 3-12: 7 FSRnH 1 0 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2010 Microchip Technology Inc. ...
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... Configuration Word 2 registers, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 8007h and Configuration Word 2 register at 8008h. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 53 ...
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... Value at POR and BOR/Value at all other Resets P = Programmable bit (1) (2) (3) Pin Function Select bit pin function is MCLR; Weak pull-up enabled. pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2010 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. 2: The entire data EEPROM will be erased when the code protection is turned off during an erase. 3: The entire program memory will be erased when the code protection is turned off. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 55 ...
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... R/P-1/1 U-1 U-1 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets P = Programmable bit (1) must be used for programming PP pin Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2010 Microchip Technology Inc. ...
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... See Section 4.5 “Device ID and Revision ID” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16F193X/LF193X/PIC16F194X/LF194X Memory Programming Specification” (DS41397). 2010 Microchip Technology Inc. PIC16F/LF1946/47 “Write such as Preliminary ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100011001 = PIC16F1946 100011010 = PIC16F1947 100011011 = PIC16LF1946 100011100 = PIC16LF1947 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. ...
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... Source (MFINTOSC) 31 kHz Source 31 kHz (LFINTOSC) 2010 Microchip Technology Inc. PIC16F/LF1946/47 The oscillator module can be configured in one of six clock modes – External clock (ECL, ECM, ECH. See Section 5.2.1.1 “EC Mode”). 2. LP – 32 kHz Low-Power Crystal mode. ...
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... Figure 5-3 and Figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. Preliminary ® MCU design is fully EXTERNAL CLOCK (EC) MODE OPERATION OSC1/CLKIN ® PIC MCU OSC2/CLKOUT (1) 2010 Microchip Technology Inc. ...
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... AN849, “Basic PIC Oscillator Design” (DS00849) ® • AN943, “Practical PIC Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) 2010 Microchip Technology Inc. PIC16F/LF1946/47 FIGURE 5- Internal Logic Sleep C2 Ceramic Resonator Note 1: A series resistor (R ceramic resonators with low drive level ...
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... PIC MCU OSC1/CLKIN Internal Clock OSC2/CLKOUT (1) 100 k, <3V EXT 3 k R 100 k, 3-5V EXT C > 20 pF, 2-5V EXT Output depends upon CLKOUTEN bit of the Configuration Word 1. ) and capacitor (C ) values EXT EXT 2010 Microchip Technology Inc. ...
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... OSCTUNE register (Register 5-3). 3. The LFINTOSC (Low-Frequency Oscillator) is uncalibrated and operates at 31 kHz. 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 5-3). ...
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... These dupli- cate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transi- tion times can be obtained between frequency changes that use the same oscillator source. Preliminary 2010 Microchip Technology Inc. ...
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... The 4xPLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4xPLL with the internal oscillator. 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.2.2.7 Internal Oscillator Clock Switch ...
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... LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock DS41414A-page 66 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync 0 Preliminary Running Running Running 2010 Microchip Technology Inc. ...
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... Word 1, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP modes. The OST does not reflect the status of the Timer1 Oscillator. 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.3.3 TIMER1 OSCILLATOR The Timer1 Oscillator is a separate crystal oscillator associated with the Timer1 peripheral ...
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... MHz (1) (1) 31.25 kHz-500 kHz (1) 31.25 kHz-16 MHz (1) 31 kHz 32 kHz 16-32 MHz Preliminary Oscillator Delay Oscillator Warm-up Delay (T ) WARM 2 cycles 1 cycle of each 1024 Clock Cycles (OST) 2 s (approx.) 1 cycle of each 1024 Clock Cycles (OST (approx.) 2010 Microchip Technology Inc. ...
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... OSC1 1022 1023 0 1 OSC2 Program Counter System Clock 2010 Microchip Technology Inc. PIC16F/LF1946/47 5.4.3 CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC< ...
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... Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. Preliminary 2010 Microchip Technology Inc. ...
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... Clock Output Clock Monitor Output (Q) OSCFIF Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Oscillator Failure Test Test Preliminary Failure ...
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... Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Note 1: Duplicate frequency derived from HFINTOSC. DS41414A-page 72 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary U-0 R/W-0/0 R/W-0/0 SCS<1:0> — bit 0 2010 Microchip Technology Inc. ...
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... LFIOFR: Low Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate 2010 Microchip Technology Inc. PIC16F/LF1946/47 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘ ...
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... CONFIG2 7:0 — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. Note 1: PIC16F1946/47 only. DS41414A-page 74 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Bit 5 ...
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... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2010 Microchip Technology Inc. PIC16F/LF1946/47 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41414A-page 75 ...
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... BOR protection is unchanged by Sleep. DD Preliminary falls below V for a DD BOR , the device BORDC Device Device Operation upon Operation upon wake-up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2010 Microchip Technology Inc. ...
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... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2010 Microchip Technology Inc. PIC16F/LF1946/47 T BORRDY BOR Protection Active (1) T PWRT < T ...
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... Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see Figure 6-4). This is useful for testing purposes or to synchronize more than one device operating in parallel. Preliminary Timer configuration. See 2010 Microchip Technology Inc. ...
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... FIGURE 6-4: RESET START-UP SEQUENCE V DD Internal POR Power Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2010 Microchip Technology Inc. PIC16F/LF1946/47 T PWRT T MCLR T OST Preliminary DS41414A-page 79 ...
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... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2010 Microchip Technology Inc. ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16F/LF1946/47 U-0 R/W/HC-1/q R/W/HC-1/q — ...
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... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. DS41414A-page 82 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 77 POR BOR SWDTEN 105 2010 Microchip Technology Inc. ...
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... A block diagram of the interrupt logic is shown in Figure 7-1 and Figure 7-2. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE From Peripheral Interrupt Logic (Figure 7-2) 2010 Microchip Technology Inc. PIC16F/LF1946/47 Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE PEIE GIE ...
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... CCP5IF CCP5IE OSFIF OSFIE TMR1IF TMR1IE TMR6IF TMR6IE C2IF C2IE C1IF C1IE EEIF EEIE BCLIF BCLIE LCDIF LCDIE DS41414A-page 84 Preliminary 2010 Microchip Technology Inc. To Interrupt Logic (Figure 7-1) ...
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... All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2010 Microchip Technology Inc. PIC16F/LF1946/47 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins ...
Page 88
... Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP PC+1 PC+2 INST(PC) NOP NOP Preliminary 0005h Inst(0004h) 0005h Inst(0004h) 0004h 0005h NOP Inst(0004h) Inst(0005h) 0004h 0005h NOP NOP Inst(0004h) 2010 Microchip Technology Inc. ...
Page 89
... Latency is the same whether Inst (PC single cycle or a 2-cycle instruction. 3: CLKOUT not available in all Oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 29.0 “Electrical Specifications”. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2010 Microchip Technology Inc. PIC16F/LF1946/ ...
Page 90
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. DS41414A-page 88 Preliminary 2010 Microchip Technology Inc. ...
Page 91
... The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state 2010 Microchip Technology Inc. PIC16F/LF1946/47 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 92
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 TMR2IE TMR1IE bit 0 2010 Microchip Technology Inc. ...
Page 93
... Disables the LCD module interrupt bit 1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 2010 Microchip Technology Inc. PIC16F/LF1946/47 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 ...
Page 94
... Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 U-0 CCP3IE TMR6IE — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 U-0 TMR4IE — bit 0 2010 Microchip Technology Inc. ...
Page 95
... Disables the MSSP2 Bus Collision Interrupt bit 0 SSP2IE: Synchronous Serial Port (MSSP2) Interrupt Enable bit 1 = Enables the MSSP2 interrupt 0 = Disables the MSSP2 interrupt 2010 Microchip Technology Inc. PIC16F/LF1946/47 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. ...
Page 96
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2010 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 97
... Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2010 Microchip Technology Inc. PIC16F/LF1946/47 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 98
... R/W-0/0 R/W-0/0 R/W-0/0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R/W-0/0 TMR4IF — bit 0 2010 Microchip Technology Inc. ...
Page 99
... Interrupt is not pending bit 0 SSP2IF: Synchronous Serial Port (MSSP2) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2010 Microchip Technology Inc. PIC16F/LF1946/47 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 100
... BCLIF LCDIF CCP4IF CCP3IF TMR6IF — RC2IF TX2IF — — Preliminary Register Bit 1 Bit 0 on Page INTF IOCIF 89 PS<2:0> 189 TMR2IE TMR1IE 90 — CCP2IE 91 TMR4IE — 92 BCL2IE SSP2IE 93 TMR2IF TMR1IF 94 — CCP2IF 95 TMR4IF — 96 BCL2IF SSP2IF 97 2010 Microchip Technology Inc. ...
Page 101
... LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F1946/47 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the V and I/O pins to operate higher voltage. There is no user enable/disable control available for the LDO always active ...
Page 102
... PIC16F/LF1946/47 NOTES: DS41414A-page 100 Preliminary 2010 Microchip Technology Inc. ...
Page 103
... See Section 16.0 “Digital-to-Analog Con- verter (DAC) Module” and Section 14.0 “Fixed Volt- age Reference (FVR)” for more information on these modules. 2010 Microchip Technology Inc. PIC16F/LF1946/47 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 104
... Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 89 IOCBF1 IOCBF0 148 IOCBN1 IOCBN0 148 IOCBP1 IOCBP0 148 TMR2IE TMR1IE 90 — CCP2IE 91 TMR4IE — 92 BCL2IE SSP2IE 93 TMR2IF TMR1IF 94 — CCP2IF 95 TMR4IF — 96 BCL2IF SSP2IF SWDTEN 105 2010 Microchip Technology Inc. ...
Page 105
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2010 Microchip Technology Inc. PIC16F/LF1946/47 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41414A-page 103 ...
Page 106
... STATUS register are changed to indicate the event. See Active Section 3.0 “Memory Organization” and STATUS Active register (Register 3-1) for more information. Disabled Active Disabled Disabled Preliminary WDT Cleared Cleared until the end of OST Unaffected 2010 Microchip Technology Inc. ...
Page 107
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 108
... PIC16F/LF1946/47 NOTES: DS41414A-page 106 Preliminary 2010 Microchip Technology Inc. ...
Page 109
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2010 Microchip Technology Inc. PIC16F/LF1946/47 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 110
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2010 Microchip Technology Inc. ...
Page 111
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) INSTR( BSF EECON1,RD executed here executed here RD bit EEDATH EEDATL Register EERHLT 2010 Microchip Technology Inc. PIC16F/LF1946/47 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 112
... NOPs. This prevents the user from executing a two-cycle instruction instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Number of Write Latches/Boundary 8 words, EEADRL<2:0> = 000 Preliminary 2010 Microchip Technology Inc. on the next ...
Page 113
... NOP ; Executed (Figure 11-1) NOP ; Ignored (Figure 11-1) BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 111 ...
Page 114
... Example 11-5. The initial address is loaded into the EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. Note: The code Example 11-5 must be repeated multiple times to fully program an erased program memory row. Preliminary 2010 Microchip Technology Inc. sequence provided in ...
Page 115
... EEADRL<3:0> = 0000 EEADRL<3:0> = 0001 Buffer Register 2010 Microchip Technology Inc. PIC16F/LF1946/47 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 write instruction. ...
Page 116
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2010 Microchip Technology Inc. ...
Page 117
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2010 Microchip Technology Inc. PIC16F/LF1946/47 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 118
... Different access may exist for reads and writes. Refer to Table 11-2. When read access is initiated on an address outside the parameters listed in Table 11-2, the EEDATH:EEDATL register pair is cleared. Function Read Access User IDs Yes Yes Yes Preliminary Write Access Yes No No 2010 Microchip Technology Inc. ...
Page 119
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2010 Microchip Technology Inc. PIC16F/LF1946/47 Preliminary DS41414A-page 117 ...
Page 120
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2010 Microchip Technology Inc. ...
Page 121
... RD: Read Control bit 1 = Initiates an program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 122
... EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCLIE LCDIE C1IF EEIF BCLIF LCDIF Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 119 107* 118 118 118 118 INTF IOCIF 89 C3IE CCP2IE 91 C3IF CCP2IF 95 2010 Microchip Technology Inc. ...
Page 123
... Write PORTx CK Data Register Data Bus Read PORTx To peripherals ANSELx 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.1 Alternate Pin Function The Alternate Pin Function Control (APFCON) register is used to steer specific peripheral input and output functions between different pins. The APFCON register is shown in Register 12-1 ...
Page 124
... P1BSEL: CCP1 PWM B Output Pin Selection bit 0 = P1B function is on RE6/P1B/COM3 1 = P1B function is on RD6/P1B/SEG6 DS41414A-page 122 R/W-0/0 R/W-0/0 R/W-0/0 P2CSEL P2BSEL CCP2SEL U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 P1CSEL P1BSEL bit 0 2010 Microchip Technology Inc. ...
Page 125
... MOVLW B'11110000' ;Set RA<7:4> as inputs MOVWF TRISA ;and set RA<3:0> as ;outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.2.2 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 126
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATA4 LATA3 LATA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RA1 RA0 bit 0 R/W-1/1 R/W-1/1 TRISA1 TRISA0 bit 0 R/W-x/u R/W-x/u LATA1 LATA0 bit 0 2010 Microchip Technology Inc. ...
Page 127
... CONFIG1 7:0 CP MCLRE Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. 2010 Microchip Technology Inc. PIC16F/LF1946/47 U-0 R/W-1/1 — ANSA3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 128
... SEG8 (LCD) RB2 1. SEG9 (LCD) RB3 1. SEG10 (LCD) RB4 1. SEG11 (LCD) RB5 1. SEG29 (LCD) 2. T1G (TMR1) RB6 Section 13.0 1. ICSPCLK (Programming) 2. ICDCLK (enabled by Configuration Word) 3. SEG38 (LCD) RB7 1. ICSPDAT (Programming) 2. ICDDAT (enabled by Configuration Word) 3. SEG39 (LCD) Preliminary 2010 Microchip Technology Inc. ...
Page 129
... Bit is cleared bit 7-0 LATB<7:0>: PORTB Output Latch Value bits Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RB4 RB3 RB2 U = Unimplemented bit, read as ‘ ...
Page 130
... IOCBF1 IOCBF0 148 LATB2 LATB1 LATB0 127 SE10 SE9 SE8 333 SE26 SE25 SE24 333 SE34 SE33 SE32 333 PS<2:0> 189 RB2 RB1 RB0 127 T1GSS<1:0> 200 TRISB2 TRISB1 TRISB0 127 WPUB2 WPUB1 WPUB0 128 2010 Microchip Technology Inc. ...
Page 131
... TRISC ; MOVLW B'11110000' ;Set RC<7:4> as inputs MOVWF TRISC ;and set RC<3:0> as ;outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions. The is TRISC pins, their combined functions and their output priorities are briefly described here ...
Page 132
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2010 Microchip Technology Inc. ...
Page 133
... TMR1CS<1:0> TX1STA CSRC TX9 TX2STA CSRC TX9 TRISC TRISC7 TRISC6 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 P2DSEL P2CSEL P2BSEL CCP2SEL LATC5 LATC4 LATC3 ...
Page 134
... P2B (CCP) 2. SEG2 (LCD) RD3 1. SEG3 (LCD) 2. P3C (CCP) RD4 1. SEG4 (LCD) 2. P3D (CCP) 3. SDO2 (SSP2) RD5 1. SEG5 (LCD) 2. P1C (CCP) 3. SDI2/SDA2 (SSP2) RD6 1. SEG5 (LCD) 2. P1B (CCP) 3. SCK2/SCL2 (SSP2) RD7 1. SEG7 (LCD) 2. SS2 (SSP2) Preliminary 2010 Microchip Technology Inc. ...
Page 135
... Bit is cleared bit 7-0 LATD<7:0>: PORTD Output Latch Value bits Note 1: Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RD4 RD3 RD2 U = Unimplemented bit, read as ‘ ...
Page 136
... CS<1:0> SE5 SE4 SE3 SE2 RD5 RD4 RD3 RD2 TRISD5 TRISD4 TRISD3 TRISD2 Preliminary Register on Bit 1 Bit 0 Page P1CSEL P1BSEL 122 229 LATD1 LATD0 133 LMUX<1:0> 329 SE1 SE0 333 RD1 RD0 133 TRISD1 TRISD0 133 2010 Microchip Technology Inc. ...
Page 137
... MOVLW B‘00001100’ ;Set RE<3:2> as inputs MOVWF TRISE ;and set RE<1:0> ;as outputs 2010 Microchip Technology Inc. PIC16F/LF1946/47 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet ...
Page 138
... Value at POR and BOR/Value at all other Resets R/W-1 R/W-1 R/W-1 TRISE4 TRISE3 TRISE2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u RE1 RE0 bit 0 R/W-1 R/W-1 TRISE1 TRISE0 bit 0 2010 Microchip Technology Inc. ...
Page 139
... TRISE TRISE7 TRISE6 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: Applies to ECCP modules only. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u LATE4 LATE3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 140
... INITIALIZING PORTF BANKSEL PORTF ; CLRF PORTF ;Init PORTF BANKSEL LATF ;Data Latch CLRF LATF ; BANKSEL ANSELF ; CLRF ANSELF ;digital I/O BANKSEL TRISF ; MOVLW B'11110000' ;Set RF<7:4> as inputs MOVWF TRISF ;and set RF<3:0> as ;outputs DS41414A-page 138 is TRISF Preliminary 2010 Microchip Technology Inc. ...
Page 141
... SRQ (SR Latch) RF3 1. AN8 (ADC) 2. CPS8 (CSM) 3. C123IN2- (Comparator) 4. SEG21 (LCD) RF4 1. AN9 (ADC) 2. CPS9 (CSM) 3. C2IN+ (Comparator) 4. SEG22 (LCD) 2010 Microchip Technology Inc. PIC16F/LF1946/47 RF5 1. AN10 (ADC) 2. CPS10 (CSM) 3. C12IN1- (Comparator) 4. DACOUT (DAC) 5. SEG23 (LCD) RF6 1. AN11 (ADC) 2. CPS11 (CSM) 3. ...
Page 142
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATF4 LATF3 LATF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RF1 RF0 bit 0 R/W-1/1 R/W-1/1 TRISF1 TRISF0 bit 0 R/W-x/u R/W-x/u LATF1 LATF0 bit 0 2010 Microchip Technology Inc. ...
Page 143
... CONFIG2 7:0 — — Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-1/1 ANSDF4 ANSF3 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) ...
Page 144
... C3IN+ (Comparator) 5. SEG44 (LCD) RG3 1. AN13 (ADC) 2. CPS13 (CSM) 3. C3IN0- (Comparator) 4. CCP4 (CCP) 5. P3D (CCP) 6. SEG45 (LCD) RG4 1. AN12 (ADC) 2. CPS12 (CSM) 3. C3IN1- (Comparator) 4. CCP5 (CCP) 5. P1D (CCP) 6. SEG26 (LCD) RG5 1. V /MCLR (Basic)SEG18 (LCD) PP Preliminary 2010 Microchip Technology Inc. ...
Page 145
... Unimplemented: Read as ‘0’. bit 5-0 LATG<5:0>: PORTG Output Latch Value bits Note 1: Writes to PORTG are actually written to corresponding LATG register. Reads from PORTG register is return of actual I/O pin values. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u RG4 RG3 RG2 U = Unimplemented bit, read as ‘ ...
Page 146
... Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-1/1 U-0 ANSG1 — bit 0 U-0 U-0 — — bit 0 2010 Microchip Technology Inc. ...
Page 147
... TRISG WPUG — — Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTG. Note 1: Applies to ECCP modules only. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — ANSG4 ANSG3 ANSG2 DCxB< ...
Page 148
... PIC16F/LF1946/47 NOTES: DS41414A-page 146 Preliminary 2010 Microchip Technology Inc. ...
Page 149
... R RBx IOCBPx 2010 Microchip Technology Inc. PIC16F/LF1946/47 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 150
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2010 Microchip Technology Inc. ...
Page 151
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Interrupt-on-Change. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF IOCBF5 IOCBF4 IOCBF3 ...
Page 152
... PIC16F/LF1946/47 NOTES: DS41414A-page 150 Preliminary 2010 Microchip Technology Inc. ...
Page 153
... FVRCON register. FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010 Microchip Technology Inc. PIC16F/LF1946/47 14.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each , with 1 ...
Page 154
... ADC Fixed Voltage Reference Peripheral output is 1x (1.024V ADC Fixed Voltage Reference Peripheral output is 2x (2.048V ADC Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: FVRRDY is always ‘1’ on devices with LDO (PIC16F1946/47). 2: Fixed Voltage Reference output cannot exceed V TABLE 14-1: ...
Page 155
... DAC FVR Buffer1 CHS<4:0> Note: When ADON = 0, all multiplexer inputs are disconnected. 2010 Microchip Technology Inc. PIC16F/LF1946/47 approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 15-1 shows the block diagram of the ADC. (ADC) ...
Page 156
... Section 29.0 “Electrical Specifications” for more information. Table 15-1 gives examples of appropriate ADC clock selections. Note: Unless using the F system clock frequency will change the ADC adversely affect the ADC result. Preliminary AD specifica any changes in the RC clock frequency, which may 2010 Microchip Technology Inc. ...
Page 157
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2010 Microchip Technology Inc. PIC16F/LF1946/ DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 158
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2010 Microchip Technology Inc. ...
Page 159
... Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2010 Microchip Technology Inc. PIC16F/LF1946/47 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 160
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2010 Microchip Technology Inc. ...
Page 161
... ADC is disabled and consumes no operating current Note 1: See Section 16.0 “Digital-to-Analog Converter (DAC) Module” for more information. 2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ ...
Page 162
... V REF connected to internal fixed voltage reference REF DS41414A-page 160 R/W-0/0 U-0 R/W-0/0 — ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS - REF DD + REF Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 2010 Microchip Technology Inc. ...
Page 163
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 164
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2010 Microchip Technology Inc. ...
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... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2010 Microchip Technology Inc. PIC16F/LF1946/47 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
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... V - REF DS41414A-page 164 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 1 LSB ideal Full-Scale Transition Analog Input Voltage 1 LSB ideal Zero-Scale V + REF Transition Preliminary HOLD REF Sampling Switch (k) 2010 Microchip Technology Inc. ...
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... FVRRDY DACCON0 DACEN DACLPS DACCON1 — — Legend unknown unchanged, — = unimplemented read as ‘0’ value depends on condition. Shaded cells are not used for ADC module. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> — ADNREF ANSA5 ANSA4 ...
Page 168
... PIC16F/LF1946/47 NOTES: DS41414A-page 166 Preliminary 2010 Microchip Technology Inc. ...
Page 169
... SRC The negative voltage source is disabled by setting the DACLPS bit in the DACCON0 register. Clearing the DACLPS bit in the DACCON0 register disables the positive voltage source. 2010 Microchip Technology Inc. PIC16F/LF1946/47 16.3.1 OUTPUT CLAMPED TO POSITIVE VOLTAGE SOURCE The DAC output voltage can be set to V ...
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... Output Clamped to Positive Voltage Source V + SRC R DACR<4:0> = 11111 R DACEN = 0 DACLPS = 1 DAC Voltage Ladder (see Figure 16- SRC DS41414A-page 168 Output Clamped to Negative Voltage Source V + SRC R R DACEN = 0 DACLPS = SRC Preliminary 2010 Microchip Technology Inc. DAC Voltage Ladder (see Figure 16-2) DACR<4:0> = 00000 ...
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... DAC voltage reference output for external connections to DACOUT. Figure 16-3 shows an example buffering technique. FIGURE 16-2: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM FVR BUFFER2 REF DACPSS<1:0> 2 DACEN DACLPS DACNSS V - REF V SS 2010 Microchip Technology Inc. PIC16F/LF1946/47 Digital-to-Analog Converter (DAC SRC Steps SRC Preliminary DACR< ...
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... Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. DS41414A-page 170 + DACOUT – Preliminary Buffered DAC Output 2010 Microchip Technology Inc. ...
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... OUT SRC SRC Note 1: The output select bits are always right justified to ensure that any number of bits can be used without affecting the register layout. 2010 Microchip Technology Inc. PIC16F/LF1946/47 U-0 R/W-0/0 R/W-0/0 — DACPSS<1:0> Unimplemented bit, read as ‘0’ ...
Page 174
... Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC Module. DS41414A-page 172 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved CDAFVR<1:0> DACOE — DACPSS<1:0> — DACR<4:0> Preliminary Register Bit 1 Bit 0 on page ADFVR<1:0> 152 — DACNSS 171 171 2010 Microchip Technology Inc. ...
Page 175
... V -, the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2010 Microchip Technology Inc. PIC16F/LF1946/47 FIGURE 17-1: SINGLE COMPARATOR – V ...
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... DS41414A-page 174 (1) Interrupt Interrupt C POL CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2010 Microchip Technology Inc. ...
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... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2010 Microchip Technology Inc. PIC16F/LF1946/47 17.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register ...
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... See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 16.0 “Digital-to-Analog (DAC) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. Preliminary Converter 2010 Microchip Technology Inc. ...
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... Analog Voltage Threshold Voltage T Note 1: See Section 29.0 “Electrical Specifications”. 2010 Microchip Technology Inc. PIC16F/LF1946/47 17.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-3. Since the analog input pins share their connection with a digital input, they have reverse ...
Page 180
... Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous DS41414A-page 178 R/W-0/0 U-0 R/W-1/1 CxPOL CxSP — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxHYS CxSYNC bit 0 2010 Microchip Technology Inc. ...
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... Unimplemented: Read as ‘0’ bit 2 MC3OUT: Mirror Copy of C3OUT bit bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-0/0 U-0 CxPCH<1:0> — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... C1HYS C1SYNC 178 C2HYS C2SYNC 178 C1NCH<1:0> 179 C2NCH<1:0> 179 C3HYS C3SYNC 178 C3NCH<1:0> 179 MC2OUT MC1OUT 179 ADFVR<1:0> 152 — DACNSS 171 171 INTF IOCIF 89 — CCP2IE 91 — CCP2IF 95 TRISF1 TRISF0 140 TRISG1 TRISG0 143 2010 Microchip Technology Inc. ...
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... Note: Enabling both the Set and Reset inputs from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2010 Microchip Technology Inc. PIC16F/LF1946/47 18.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 184
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E Note and simultaneously Pulse generator causes a 1 Q-state pulse width. 3: Name denotes the connection point at the comparator output. DS41414A-page 182 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2010 Microchip Technology Inc. SRQ SRNQ ...
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... Pulse set input for 1 Q-clock period effect on set input bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse reset input for 1 Q-clock period effect on reset input Note 1: Set only, always reads back ‘ 0 ’. 2010 Microchip Technology Inc. PIC16F/LF1946/ MHz MHz OSC OSC 39 ...
Page 186
... C1 Comparator output has no effect on the reset input of the SR Latch DS41414A-page 184 R/W-0/0 R/W-0/0 R/W-0/0 SRSC1E SRRPE SRRCKE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 2010 Microchip Technology Inc. ...
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... SRCON0 SRLEN SRCLK<2:0> SRCON1 SRSPE SRSCKE TRISA TRISA7 TRISA6 Legend: — = unimplemented location, read as ‘0’. Shaded cells are unused by the SR Latch module. 2010 Microchip Technology Inc. PIC16F/LF1946/47 Bit 5 Bit 4 Bit 3 Bit 2 ANSA5 ANSA4 ANSA3 ANSA2 SRQEN SRNQEN ...
Page 188
... PIC16F/LF1946/47 NOTES: DS41414A-page 186 Preliminary 2010 Microchip Technology Inc. ...
Page 189
... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2010 Microchip Technology Inc. PIC16F/LF1946/47 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
Page 190
... Section 29.0 “Electrical Specifications”. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41414A-page 188 Preliminary 2010 Microchip Technology Inc. ...
Page 191
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2010 Microchip Technology Inc. PIC16F/LF1946/47 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 192
... PIC16F/LF1946/47 NOTES: DS41414A-page 190 Preliminary 2010 Microchip Technology Inc. ...
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... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2010 Microchip Technology Inc. PIC16F/LF1946/47 • Gate Toggle Mode • Gate Single-pulse Mode • Gate Value Status • Gate Event Interrupt Figure 20 block diagram of the Timer1 module ...
Page 194
... T1CKI is low. T1OSCEN System Clock ( OSC Instruction Clock (F x OSC Capacitive Sensing Oscillator x External Clocking on T1CKI Pin 0 Osc.Circuit On T1OSI/T1OSO Pins 1 Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2010 Microchip Technology Inc. ...
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... A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2010 Microchip Technology Inc. PIC16F/LF1946/47 20.6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 Gate circuitry ...
Page 196
... TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 Gate is not enabled (TMR1GE bit is cleared). Preliminary 2010 Microchip Technology Inc. ...
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... T1CKI = 0 when TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. PIC16F/LF1946/47 20.9 ECCP/CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode ...
Page 198
... PIC16F/LF1946/47 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 20-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41414A-page 196 Preliminary 2010 Microchip Technology Inc ...
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... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF 2010 Microchip Technology Inc. PIC16F/LF1946/47 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41414A-page 197 ...
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... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41414A-page 198 Set by hardware on falling edge of T1GVAL Preliminary 2010 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...