ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 27

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.1.4
6.1.5
6.2
6.2.1
6.2.2
9157B–AVR–01/10
Clock Sources
Analog to Digital Converter Clock – clk
High-Speed Two-Wire Interface Clock – clk
Default Clock Source
Clock Startup Sequence
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
The TWI clock controls the operation of the Two-Wire Interface module, when operated in
high-speed mode. In practice, this clock is identical to the source clock of the device. See
Rate Generator Unit” on page
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Note:
The device is shipped with internal oscillator at 8.0 MHz and with the fuse CKDIV8 programmed,
resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out period
enabled (CKSEL = 0b10, SUT = 0b10, CKDIV8 = 0). The default setting ensures that all users
can make their desired clock source setting using any available programming interface.
Any clock source needs a sufficient V
cycles before it can be considered stable.
To ensure sufficient V
the device reset is released by all other reset sources.
describes the start conditions for the internal reset. The delay (t
oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in
and temperature dependent, as shown in
dog Oscillator Frequency vs. Temperature” on page
1. For all fuses “1” means unprogrammed while “0” means programmed.
CKSEL1..0
Device Clocking Options
00
01
10
11
CC
, the device issues an internal reset with a time-out delay (t
ADC
TWIHS
134.
Table
Device Clocking Option
External Clock
Reserved
Calibrated Internal Oscillator
Internal 128 kHz Oscillator
CC
6-2. The frequency of the Watchdog oscillator is voltage
(1)
to start oscillating and a minimum number of oscillating
“Internal Oscillator Speed” on page 228
228.
ATtiny88 Automotive
“System Control and Reset” on page 40
TOUT
) is timed from the Watchdog
and
TOUT
“Watch-
) after
“Bit
27