PIC18F45K20-I/P Microchip Technology, PIC18F45K20-I/P Datasheet - Page 150
![IC PIC MCU FLASH 16KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F45K20-I/P
Manufacturer Part Number
PIC18F45K20-I/P
Description
IC PIC MCU FLASH 16KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F45K20-IPT.pdf
(78 pages)
6.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F45K20-I/P
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
35
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
14-ch x 10-bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240313 - BOARD DEMO 8BIT XLPAC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPDM164124 - KIT STARTER FOR PIC18F4XK20
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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- PIC18F25K20T-ISS PDF datasheet
- PIC18F25K20T-ISS PDF datasheet #2
- PIC18F25K20T-ISS PDF datasheet #3
- PIC18F25K20T-ISS PDF datasheet #4
- PIC18F45K20-IPT PDF datasheet #5
- PIC18F26K20-ISO PDF datasheet #6
- Current page: 150 of 430
- Download datasheet (7Mb)
PIC18F2XK20/4XK20
11.4.1
The PWM period is specified by the PR2 register of
Timer2. The PWM period can be calculated using the
formula of Equation 11-1.
EQUATION 11-1:
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCPx pin is set. (Exception: If the PWM duty
• The PWM duty cycle is latched from CCPR
DS41303D-page 148
cycle = 0%, the pin will not be set.)
CCPR
Note:
Note: T
PWM Period
x
H.
PWM PERIOD
The Timer2 postscaler (see Section 14.1
“Timer2 Operation”) is not used in the
determination of the PWM frequency.
OSC
= 1/F
=
(TMR2 Prescale Value)
[
PWM PERIOD
(
OSC
PR2
.
)
+
1
] 4 T
•
•
OSC
•
x
L into
Preliminary
11.4.2
The PWM duty cycle is specified by writing a 10-bit
value to multiple registers: CCPR
DCxB<1:0> bits of the CCPxCON register. The
CCPR
bits of the CCPxCON register contain the two LSbs.
CCPR
register can be written to at any time. The duty cycle
value is not latched into CCPR
completes (i.e., a match between PR2 and TMR2
registers occurs). While using the PWM, the CCPR
register is read-only.
Equation 11-2 is used to calculate the PWM pulse
width.
Equation 11-3 is used to calculate the PWM duty cycle
ratio.
EQUATION 11-2:
EQUATION 11-3:
The CCPR
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
The 8-bit timer TMR2 register is concatenated with
either the 2-bit internal system clock (F
the prescaler, to create the 10-bit time base. The system
clock is used if the Timer2 prescaler is set to 1:1.
When the 10-bit time base matches the CCPR
2-bit latch, then the CCPx pin is cleared (see
Figure 11-3).
Duty Cycle Ratio
x
x
Pulse Width
L contains the eight MSbs and the DCxB<1:0>
L and DCxB<1:0> bits of the CCPxCON
x
PWM DUTY CYCLE
H register and a 2-bit internal latch are
=
T
OSC
(
=
PULSE WIDTH
DUTY CYCLE RATIO
CCPRxL:DCxB<1:0>
© 2008 Microchip Technology Inc.
(
---------------------------------------------------------- -
CCPRxL:DCxB<1:0>
•
(TMR2 Prescale Value)
4 PR2
x
H until after the period
(
x
+
OSC
L register and
1
)
), or 2 bits of
)
•
)
x
H and
x
H
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