PIC16F916-I/SP Microchip Technology, PIC16F916-I/SP Datasheet - Page 233

• Manufacturer Part Number: PIC16F916-I/SP
• Description: IC PIC MCU FLASH 8KX14 28SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F916-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 14KB (8K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 352 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 352 B
• Interface Type: SSP/I2C/AUSART/SPI
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.3.1
External interrupt on RB0/INT/SEG0 pin is edge-trig-
gered; either rising if the INTEDG bit of the OPTION
register is set, or falling, if the INTEDG bit is clear.
When a valid edge appears on the RB0/INT/SEG0 pin,
the INTF bit of the INTCON register is set. This inter-
rupt can be disabled by clearing the INTE control bit of
the INTCON register. The INTF bit must be cleared in
software in the Interrupt Service Routine before
re-enabling this interrupt. The RB0/INT/SEG0 interrupt
can wake-up the processor from Sleep if the INTE bit
was set prior to going into Sleep. The status of the GIE
bit decides whether or not the processor branches to
the interrupt vector following wake-up (0004h). See
Section 16.5 “Power-Down Mode (Sleep)” for details
on Sleep and Figure 16-10 for timing of wake-up from
Sleep through RB0/INT/SEG0 interrupt.
FIGURE 16-7:
© 2007 Microchip Technology Inc.
RB0/INT/SEG0 INTERRUPT
IOC-RB4
IOC-RB5
IOC-RB6
IOC-RB7
TMR2IF
TMR2IE
TMR1IE
TMR1IF
CCP1IF
CCP1IE
CCP2IF
CCP2IE
OSFIF
OSFIE
SSPIF
SSPIE
LCDIF
LCDIE
LVDIF
LVDIE
IOCB4
IOCB5
IOCB6
IOCB7
RCIF
RCIE
ADIF
ADIE
EEIE
C1IF
C1IE
C2IF
C2IE
EEIF
TXIF
TXIE
INTERRUPT LOGIC
*
PIC16F913/914/916/917/946
TMR0IF
TMR0IE
RBIE
INTF
INTE
RBIF
PEIF
PEIE
GIE
16.3.2
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF bit of the INTCON register. The interrupt can
be enabled/disabled by setting/clearing T0IE bit of the
INTCON register. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
16.3.3
An input change on PORTB change sets the RBIF bit
of the INTCON register. The interrupt can be
enabled/disabled by setting/clearing the RBIE bit of the
INTCON register. Plus, individual pins can be
configured through the IOCB register.
Note:
* Only available on the PIC16F914/917.
TMR0 INTERRUPT
PORTB INTERRUPT
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
Wake-up (If in Sleep mode)
Interrupt to CPU
DS41250F-page 231