PIC18F46J11-I/PT Microchip Technology, PIC18F46J11-I/PT Datasheet - Page 449

• Manufacturer Part Number: PIC18F46J11-I/PT
• Description: IC PIC MCU FLASH 64KB 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F46J11-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 34
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.2
In addition to the standard 75 instructions of the PIC18
instruction set, the PIC18F46J11 family of devices also
provides an optional extension to the core CPU func-
tionality. The added features include eight additional
instructions that augment Indirect and Indexed
Addressing operations and the implementation of
Indexed Literal Offset Addressing for many of the
standard PIC18 instructions.
The additional features of the extended instruction
set are enabled by default on unprogrammed
devices. Users must properly set or clear the XINST
Configuration bit during programming to enable or
disable these features.
The instructions in the extended set can all be
classified as literal operations, which either manipulate
the File Select Registers (FSR), or use them for
Indexed Addressing. Two of the instructions, ADDFSR
and SUBFSR, each have an additional special instanti-
ation for using FSR2. These versions (ADDULNK and
SUBULNK) allow for automatic return after execution.
The extended instructions are specifically implemented
to optimize re-entrant program code (that is, code that
is recursive or that uses a software stack) written in
high-level languages, particularly C. Among other
things, they allow users working in high-level
languages to perform certain operations on data
structures more efficiently. These include:
• Dynamic allocation and deallocation of software
• Function Pointer invocation
• Software Stack Pointer manipulation
• Manipulation of variables located in a software
TABLE 26-3:
© 2009 Microchip Technology Inc.
ADDFSR
ADDULNK
CALLW
MOVSF
MOVSS
PUSHL
SUBFSR
SUBULNK
stack space when entering and leaving
subroutines
stack
Mnemonic,
Operands
Extended Instruction Set
f, k
k
z
z
k
f, k
k
s
s
, f
, z
d
EXTENSIONS TO THE PIC18 INSTRUCTION SET
d
Add Literal to FSR
Add Literal to FSR2 and Return
Call Subroutine using WREG
Move z
Move z
Store Literal at FSR2,
Subtract Literal from FSR
Subtract Literal from FSR2 and
Decrement FSR2
Return
f
z
d
s
s
d
(destination) 2nd word
(source) to
(source) to
(destination) 2nd word
Description
1st word
1st word
Cycles
1
2
2
2
2
1
1
2
PIC18F46J11 FAMILY
A summary of the instructions in the extended instruc-
tion set is provided in Table 26-3. Detailed descriptions
are provided in Section 26.2.2 “Extended Instruction
Set”. The opcode field descriptions in Table 26-1
(page 408) apply to both the standard and extended
PIC18 instruction sets.
26.2.1
Most of the extended instructions use indexed argu-
ments, using one of the FSRs and some offset to specify
a source or destination register. When an argument for
an instruction serves as part of Indexed Addressing, it is
enclosed in square brackets (“[ ]”). This is done to indi-
cate that the argument is used as an index or offset. The
MPASM™ Assembler will flag an error if it determines
that an index or offset value is not bracketed.
When the extended instruction set is enabled, brackets
are also used to indicate index arguments in
byte-oriented and bit-oriented instructions. This is in
addition to other changes in their syntax. For more
details, see Section 26.2.3.1 “Extended Instruction
Syntax with Standard PIC18 Commands”.
Note:
Note:
1110
1110
0000
1110
1111
1110
1111
1110
1110
1110
MSb
16-Bit Instruction Word
The instruction set extension and the
Indexed Literal Offset Addressing mode
were designed for optimizing applications
written in C; the user may likely never use
these instructions directly in assembler.
The syntax for these commands is
provided as a reference for users who may
be
generated by a compiler.
EXTENDED INSTRUCTION SYNTAX
In the past, square brackets have been
used to denote optional arguments in the
PIC18 and earlier instruction sets. In this
text
arguments are denoted by braces (“{ }”).
1000
1000
0000
1011
ffff
1011
xxxx
1010
1001
1001
reviewing
and
0zzz
ffff
1zzz
xzzz
kkkk
ffkk
11kk
ffkk
11kk
0001
going
code
kkkk
kkkk
0100
zzzz
ffff
zzzz
zzzz
kkkk
kkkk
kkkk
LSb
forward,
DS39932C-page 449
that
Affected
Status
has
None
None
None
None
None
None
None
None
—
—
—
optional
been