PIC18F2431-I/SO Microchip Technology, PIC18F2431-I/SO Datasheet - Page 17

• Manufacturer Part Number: PIC18F2431-I/SO
• Description: IC PIC MCU FLASH 8KX16 28SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2431-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 16KB (8K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART/I2C/SPI/SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 5-ch x 10-bit
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28SO-1 - SOCKET TRANSITION 28SOIC 300MILI3-DB18F4431 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair EEADR:EEADRH) and a
data latch (EEDATA). Data EEPROM is written by load-
ing EEADR:EEADRH with the desired memory loca-
tion, EEDATA with the data to be written, and initiating
a memory write by appropriately configuring the
EECON1 and EECON2 registers. A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh, immediately prior to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th SCLK
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, SCLK
must still be held low for the time specified by
parameter P10 to allow high voltage discharge of the
memory array.
FIGURE 3-8:
 2010 Microchip Technology Inc.
SCLK
SDATA
Poll WR bit
4-bit Command
Data EEPROM Programming
1
0
2
0
3
0
SDATA
4
SCLK
0
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
4-bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
PIC18F2331/2431/4331/4431
2
SDATA = Input
SDATA = Input
15 16
P5A
4-bit Command
Poll WR bit, Repeat until Clear
1
0
FIGURE 3-7:
2
0
3
0
(see below)
4
0
P5
MOVWF TABLAT
1
No
2
Unlock Sequence
15 16
55h - EECON2
AAh - EECON2
PROGRAM DATA FLOW
Enable Write
Set Address
Start Write
Sequence
Set Data
WR bit
Clear ?
Done
Start
Done
P5A
?
Yes
Yes
(see Figure 4-4)
Shift Out Data
SDATA = Output
DS30500B-page 17
No
P10
16-bit Data
Payload
1
n
2
n