PIC16C64A-04I/L Microchip Technology, PIC16C64A-04I/L Datasheet - Page 48

IC MCU OTP 2KX14 PWM 44PLCC

PIC16C64A-04I/L

Manufacturer Part Number
PIC16C64A-04I/L
Description
IC MCU OTP 2KX14 PWM 44PLCC
Manufacturer
Microchip Technology
Series
PIC® 16Cr

Specifications of PIC16C64A-04I/L

Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Core Processor
PIC
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Controller Family/series
PIC16C
No. Of I/o's
33
Ram Memory Size
128Byte
Cpu Speed
4MHz
No. Of Timers
3
No. Of Pwm Channels
1
Embedded Interface Type
I2C, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
PIC16C64A-04I/LR
PIC16C64A-04I/LR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16C64A-04I/L
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC16C6X
4.3
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any reset, the upper bits of the PC
will be cleared. Figure 4-24 shows the two situations for
the loading of the PC. The upper example in the figure
shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
ure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3>
FIGURE 4-24: LOADING OF PC IN
4.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 word block). Refer to the
application note “Implementing a Table Read” (AN556).
4.3.2
The PIC16CXX family has an 8 deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or a POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
DS30234D-page 48
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
PC
PC
12
12 11 10
2
5
PCL and PCLATH
COMPUTED GOTO
STACK
PCH
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
DIFFERENT SITUATIONS
PCH). The lower example in the fig-
7
7
PCL
PCL
PCH).
11
8
0
0
Instruction with
PCL as
ALU
GOTO, CALL
Opcode <10:0>
destination
4.4
PIC16C6X devices are capable of addressing a contin-
uous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction the upper two
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruction, the user must
ensure that the page select bits are programmed so
that the desired program memory page is addressed. If
a return from a CALL instruction (or interrupt) is exe-
cuted, the entire 13-bit PC is pushed onto the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instructions (which POPs the
address from the stack).
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
Note:
Note 1: There are no status bits to indicate stack
Note 2: There are no instructions mnemonics
Program Memory Paging
PIC16C6X devices with 4K or less of pro-
gram
PCLATH<4>. The use of PCLATH<4> as a
general purpose read/write bit is not rec-
ommended since this may affect upward
compatibility with future products.
overflows or stack underflow conditions.
called PUSH or POP. These are actions
that occur from the execution of the CALL,
RETURN, RETLW, and RETFIE instruc-
tions, or the vectoring to an interrupt
address
memory
1997 Microchip Technology Inc.
ignore
paging
bit

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