PIC16C64A-04I/L Microchip Technology, PIC16C64A-04I/L Datasheet - Page 49

• Manufacturer Part Number: PIC16C64A-04I/L
• Description: IC MCU OTP 2KX14 PWM 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C64A-04I/L

• Core Size: 8-Bit
• Program Memory Size: 3.5KB (2K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-PLCC
• Controller Family/series: PIC16C
• No. Of I/o's: 33
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 1
• Embedded Interface Type: I2C, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCC444-1001 - DEMO BOARD FOR PICMICRO MCUDVA16XL441 - ADAPTER DEVICE ICE 44PLCC309-1040 - ADAPTER 44-PLCC ZIF TO 40-DIP309-1039 - ADAPTER 44-PLCC TO 40-DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: PIC16C64A-04I/LR; PIC16C64A-04I/LR

Example 4-1 shows the calling of a subroutine in
page 1 of the program memory. This example assumes
that the PCLATH is saved and restored by the interrupt
service routine (if interrupts are used).
EXAMPLE 4-1:
ORG 0x500
BSF
BCF
CALL
ORG 0x900
SUB1_P1:
RETURN
FIGURE 4-25: DIRECT/INDIRECT ADDRESSING
1997 Microchip Technology Inc.
bank select
RP1: RP0
For memory map detail see Figure 4-5, Figure 4-6, Figure 4-7, and Figure 4-8.
PCLATH,3
PCLATH,4
SUB1_P1
:
:
:
:
:
Direct Addressing
location select
6
Data
Memory
CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
;Select page 1 (800h-FFFh)
;Only on >4K devices
;Call subroutine in
;page 1 (800h-FFFh)
;called subroutine
;page 1 (800h-FFFh)
;return to Call subroutine
;in page 0 (000h-7FFh)
from opcode
00h
7Fh
Bank 0
00
0
80h
FFh
Bank 1
01
100h
17Fh
Bank 2
10
4.5
The INDF register is not a physical register. Address-
ing the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF reg-
ister. Any instruction using the INDF register actually
accesses the register pointed to by the File Select Reg-
ister, FSR. Reading the INDF register itself indirectly
(FSR = '0') will produce 00h. Writing to the INDF regis-
ter indirectly results in a no-operation (although status
bits may be affected). An effective 9-bit address is
obtained by concatenating the 8-bit FSR register and
the IRP bit (STATUS<7>), as shown in Figure 4-25.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-2.
EXAMPLE 4-2:
NEXT
CONTINUE
Applicable Devices
61 62 62A R62 63 R63 64 64A R64 65 65A R65 66 67
180h
1FFh
Bank 3
11
Indirect Addressing, INDF and FSR
Registers
clrf
movlw
movwf
incf
btfss
goto
:
IRP
bank select
7
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR,F
FSR,4
NEXT
Indirect Addressing
PIC16C6X
;clear INDF register
;initialize pointer
;
;inc pointer
;all done?
;NO, clear next
;YES, continue
FSR
to RAM
DS30234D-page 49
location select
0