AT32UC3A0128-ALUR Atmel, AT32UC3A0128-ALUR Datasheet - Page 527

• Manufacturer Part Number: AT32UC3A0128-ALUR
• Description: MCU AVR32 128K FLASH 144LQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A0128-ALUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 109
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Package: 144LQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 66 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 69
• Interface Type: Ethernet/I2S/JTAG/SPI/TWI/USART
• Number Of Timers: 3
• For Use With: ATEVK1105 - KIT EVAL FOR AT32UC3A0ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 30-27. Example of an OUT Pipe with 1 Data Bank
Figure 30-28. Example of an OUT Pipe with 2 Data Banks and no Bank Switching Delay
Figure 30-29. Example of an OUT Pipe with 2 Data Banks and a Bank Switching Delay
30.7.3.12
32058J–AVR32–04/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI
FIFOCON
CRC Error
SW
SW
write data to CPU
SW
This error exists only for isochronous IN pipes. It raises the CRC Error interrupt (CRCERRI),
what triggers a PXINT interrupt if CRCERRE = 1.
A CRC error can occur during IN stage if the USB controller detects a corrupted received packet.
The IN packet is stored in the bank as if no CRC error had occurred (RXINI is raised).
write data to CPU
write data to CPU
BANK 0
BANK 0
BANK 0
SW
SW
SW
OUT
OUT
OUT
SW
SW
write data to CPU
(bank 0)
write data to CPU
DATA
BANK 1
(bank 0)
DATA
(bank 0)
BANK 1
DATA
ACK
HW
SW
HW
ACK
HW
ACK
SW
OUT
SW
SW
OUT
write data to CPU
SW
write data to CPU
(bank 1)
write data to CPU
DATA
BANK0
BANK 0
BANK0
(bank 1)
DATA
ACK
AT32UC3A
SW
OUT
ACK
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