PIC18F8621T-I/PT Microchip Technology, PIC18F8621T-I/PT Datasheet - Page 219
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PIC18F8621T-I/PT
Manufacturer Part Number
PIC18F8621T-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F8621T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8621T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 219 of 396
- Download datasheet (8Mb)
19.1
The BRG is a dedicated 8-bit or 16-bit generator that
supports both the Asynchronous and Synchronous
modes of the EUSART. By default, the BRG operates
in 8-bit mode; setting the BRG16 bit (BAUDCONx<3>)
selects 16-bit mode.
The SPBRGHx:SPBRGx register pair controls the
period of a free running timer. In Asynchronous mode,
bits BRGH (TXSTAx<2>) and BRG16 also control the
baud rate. In Synchronous mode, bit BRGH is ignored.
Table 19-1 shows the formula for computation of the
baud rate for different EUSART modes which only
apply in Master mode (internally generated clock).
Given the desired baud rate and F
integer value for the SPBRGHx:SPBRGx registers can
be calculated using the formulas in Table 19-1. From
TABLE 19-1:
EXAMPLE 19-1:
TABLE 19-2:
2005 Microchip Technology Inc.
Legend: x = Don’t care, n = value of SPBRGHx:SPBRGx register pair
TXSTAx
RCSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
For a device with F
Desired Baud Rate = F
Solving for SPBRGHx:SPBRGx:
Calculated Baud Rate = 16000000/(64 (25 + 1))
Error
Name
SYNC
0
0
0
0
1
1
X
EUSART Baud Rate Generator
(BRG)
=
=
=
=
=
=
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used by the BRG.
Configuration Bits
Enhanced USARTx Baud Rate Generator Register High Byte
Enhanced USARTx Baud Rate Generator Register Low Byte
CSRC
SPEN
Bit 7
((F
((16000000/9600)/64) – 1
[25.042] = 25
9615
(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate
(9615 – 9600)/9600 = 0.16%
—
BAUD RATE FORMULAS
BRG16
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
OSC
OSC
0
0
1
1
0
1
/Desired Baud Rate)/64) – 1
CALCULATING BAUD RATE ERROR
OSC
RCIDL
of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:
Bit 6
TX9
RX9
/(64 ([SPBRGHx:SPBRGx] + 1))
SREN
TXEN
BRGH
Bit 5
—
0
1
0
1
x
x
OSC
, the nearest
SYNC
CREN
SCKP
Bit 4
PIC18F6525/6621/8525/8621
SENDB
ADDEN
BRG16
BRG/EUSART Mode
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Synchronous
Bit 3
8-bit/Synchronous
BRGH
FERR
Bit 2
this, the error in baud rate can be determined. An
example calculation is shown in Example 19-1. Typical
baud rates and error values for the various Asynchro-
nous modes are shown in Table 19-2. It may be
advantageous to use the high baud rate (BRGH = 1) or
the 16-bit BRG to reduce the baud rate error, or
achieve a slow baud rate for a fast oscillator frequency.
Writing a new value to the SPBRGHx:SPBRGx regis-
ters causes the BRG timer to be reset (or cleared). This
ensures the BRG does not wait for a timer overflow
before outputting the new baud rate.
19.1.1
The data on the RXx pin (either RC7/RX1/DT1 or RG2/
RX2/DT2) is sampled three times by a majority detect
circuit to determine if a high or a low level is present at
the RXx pin.
—
OERR
TRMT
WUE
Bit 1
SAMPLING
ABDEN
RX9D
TX9D
Bit 0
Baud Rate Formula
0000 0010
0000 000x
-1-0 0-00
0000 0000
0000 0000
POR, BOR
F
F
Value on
F
OSC
OSC
OSC
/[64 (n + 1)]
/[16 (n + 1)]
/[4 (n + 1)]
DS39612B-page 217
other Resets
Value on all
0000 0010
0000 000x
-1-0 0-00
0000 0000
0000 0000
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