PIC18F8621T-I/PT Microchip Technology, PIC18F8621T-I/PT Datasheet - Page 392
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PIC18F8621T-I/PT
Manufacturer Part Number
PIC18F8621T-I/PT
Description
IC PIC MCU FLASH 32KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F8621T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
69
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
16 bit
For Use With
XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F8621T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 392 of 396
- Download datasheet (8Mb)
PIC18F6525/6621/8525/8621
Timing Specifications ........................................................ 337
DS39612B-page 390
Slave Synchronization .............................................. 179
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) .......................................... 178
SPI Mode (Slave Mode with CKE = 0) ...................... 180
SPI Mode (Slave Mode with CKE = 1) ...................... 180
Stop Condition Receive or Transmit Mode ............... 206
Synchronous Reception
Synchronous Transmission....................................... 227
Synchronous Transmission (Through TXEN) ........... 228
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Time-out Sequence on Power-up (MCLR
Timer0 and Timer1 External Clock ........................... 342
Timing for Transition Between Timer1 and
Timing for Transition Between Timer1 and
Transition Between Timer1 and
Transition Between Timer1 and
Transition from OSC1 to Timer1 Oscillator ................. 26
Wake-up from Sleep via Interrupt ............................. 270
A/D Conversion Requirements ................................. 355
Capture/Compare/PWM Requirements .................... 343
CLKO and I/O Requirements .................................... 338
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode
via 1 kΩ Resistor)................................................ 38
(Master Mode, SREN)....................................... 229
(MCLR Tied to V
Not Tied to V
Not Tied to V
Tied to V
OSC1 (EC with PLL Active, SCS1 = 1)............... 27
OSC1 (HS with PLL Active, SCS1 = 1)............... 27
OSC1 (HS, XT, LP)............................................. 26
OSC1 (RC, EC)................................................... 28
Requirements.................................................... 353
Requirements.................................................... 353
(Master Mode, CKE = 0) ................................... 345
(Master Mode, CKE = 1) ................................... 346
(Slave Mode, CKE = 0) ..................................... 347
Requirements (CKE = 1)................................... 348
DD
via 1 kΩ Resistor) ............................ 37
DD
DD
): Case 1 .................................... 37
): Case 2 .................................... 37
DD
via 1 kΩ Resistor) ............... 38
DD
TRISE Register
TSTFSZ ............................................................................ 315
Two-Word Instructions
TXSTAx Register
V
Voltage Reference Specifications..................................... 332
W
Wake-up from Sleep ................................................. 259, 269
Watchdog Timer (WDT)............................................ 259, 267
WCOL ....................................................... 201, 202, 203, 206
WCOL Status Flag.................................... 201, 202, 203, 206
WWW, On-Line Support ....................................................... 5
X
XORLW............................................................................. 315
XORWF ............................................................................ 316
External Clock Requirements ................................... 337
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements............................. 344
PLL Clock ................................................................. 338
Program Memory Read Requirements ..................... 339
Program Memory Write Requirements ..................... 340
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External
PSPMODE Bit................................................... 111, 128
Example Cases........................................................... 46
BRGH Bit .................................................................. 217
Using Interrupts ........................................................ 269
Associated Registers ................................................ 268
Control Register........................................................ 267
Postscaler ................................................................. 268
Programming Considerations ................................... 267
RC Oscillator............................................................. 267
Time-out Period ........................................................ 267
2
2
C Bus Data Requirements (Slave Mode) ............... 350
C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 349
Requirements ................................................... 351
Start-up Timer, Power-up Timer
and Brown-out Reset Requirements ................ 341
Clock Requirements ......................................... 342
2
2
C Bus Data Requirements ................. 352
C Bus Start/Stop Bits
2005 Microchip Technology Inc.
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