PIC18F6621-E/PT Microchip Technology, PIC18F6621-E/PT Datasheet - Page 48
![IC PIC MCU FLASH 32KX16 64TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6621-E/PT
Manufacturer Part Number
PIC18F6621-E/PT
Description
IC PIC MCU FLASH 32KX16 64TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F6525-IPT.pdf
(396 pages)
3.PIC18F6525-IPT.pdf
(8 pages)
4.PIC18F6525-IPT.pdf
(38 pages)
Specifications of PIC18F6621-E/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
MSSP, SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
53
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6621-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F6525-IPT PDF datasheet #2
- PIC18F6525-IPT PDF datasheet #3
- PIC18F6525-IPT PDF datasheet #4
- Current page: 48 of 396
- Download datasheet (8Mb)
PIC18F6525/6621/8525/8621
4.7.1
The PIC18F6525/6621/8525/8621 devices have four
two-word instructions: MOVFF, CALL, GOTO and LFSR.
The second word of these instructions has the 4 MSBs
set to ‘1’s and is a special kind of NOP instruction. The
lower 12 bits of the second word contain data to be
used by the instruction. If the first word of the instruction
is executed, the data in the second word is accessed.
EXAMPLE 4-3:
4.8
Look-up tables are implemented two ways. These are:
• Computed GOTO
• Table Reads
4.8.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL).
A look-up table can be formed with an ADDWF PCL
instruction and a group of RETLW 0xnn instructions.
WREG is loaded with an offset into the table before exe-
cuting a call to that table. The first instruction of the called
EXAMPLE 4-4:
DS39612B-page 46
CASE 1:
Object Code
CASE 2:
Object Code
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
0110 0110 0000 0000
1100 0001 0010 0011
1111 0100 0101 0110
0010 0100 0000 0000
MAIN: ORG
…
TABLE MOVF
Look-up Tables
MOVLW 0x00
CALL
ORG
RLNCF W, W
ADDWF PCL
RETLW ‘A’
RETLW ‘B’
RETLW ‘C’
RETLW ‘D’
RETLW ‘E’
END
TWO-WORD INSTRUCTIONS
COMPUTED GOTO
0x0000
TABLE
0x8000
PCL, F
TWO-WORD INSTRUCTIONS
COMPUTED GOTO USING AN OFFSET VALUE
; A simple read of PCL will update PCLATH, PCLATU
; Multiply by 2 to get correct offset in table
; Add the modified offset to force jump into table
Source Code
TSTFSZ
MOVFF
Source Code
TSTFSZ
ADDWF
ADDWF
MOVFF
REG1
REG1, REG2 ; No, execute 2-word instruction
REG3
REG1
REG1, REG2 ; Yes
REG3
; is RAM location 0?
; 2nd operand holds address of REG2
; continue code
; is RAM location 0?
; 2nd operand becomes NOP
; continue code
If the second word of the instruction is executed by itself
(first word was skipped), it will execute as a NOP. This
action is necessary when the two-word instruction is
preceded by a conditional instruction that changes the
PC. A program example that demonstrates this concept
is shown in Example 4-3. Refer to Section 25.0
“Instruction Set Summary” for further details of the
instruction set.
routine is the ADDWF PCL instruction. The next instruction
executed will be one of the RETLW 0xnn instructions that
returns the value 0xnn to the calling function.
The offset value (value in WREG) specifies the number
of bytes that the program counter should advance.
In this method, only one data byte may be stored in
each instruction location and room on the return
address stack is required.
Note:
The ADDWF
update PCLATH and PCLATU. A read
operation on PCL must be performed to
update PCLATH and PCLATU.
2005 Microchip Technology Inc.
PCL instruction does not
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