PIC18F6720T-I/PT Microchip Technology, PIC18F6720T-I/PT Datasheet - Page 283
![IC MCU FLASH 64KX16 W/AD 64-TQFP](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18F6720T-I/PT
Manufacturer Part Number
PIC18F6720T-I/PT
Description
IC MCU FLASH 64KX16 W/AD 64-TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(40 pages)
4.PIC18F6620-IPT.pdf
(14 pages)
5.PIC18F6620-IPT.pdf
(12 pages)
Specifications of PIC18F6720T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3.75 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
2 x 8 bit
Operating Supply Voltage
4.2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
For Use With
MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F6720T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F8520T-IPT PDF datasheet #2
- PIC18F8520T-IPT PDF datasheet #3
- PIC18F6620-IPT PDF datasheet #4
- PIC18F6620-IPT PDF datasheet #5
- Current page: 283 of 380
- Download datasheet (7Mb)
INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
PC
If CNT
PC
No
No
No
Q1
Q1
Q1
PIC18F6520/8520/6620/8620/6720/8720
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if 0
[ label ]
0
d
a
(f) + 1
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
No
No
No
Q2
Q2
Q2
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
f
[0,1]
[0,1]
by a 2-word instruction.
255
dest,
INCFSZ
:
:
INCFSZ
11da
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
ffff
f [,d [,a]
CNT, 1, 0
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
REG
If REG
PC
If REG
PC
Q1
Q1
Q1
=
=
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if not 0
[ label ]
0
d
a
(f) + 1
skip if result
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction which is already fetched
is discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
No
No
No
Q2
Q2
Q2
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
f
[0,1]
[0,1]
255
by a 2-word instruction.
dest,
INFSNZ
INFSNZ
10da
operation
operation
operation
Process
Data
0
No
No
No
Q3
Q3
Q3
DS39609B-page 281
REG, 1, 0
ffff
f [,d [,a]
destination
operation
operation
operation
Write to
No
No
No
Q4
Q4
Q4
ffff
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