PIC18F4685-I/PT Microchip Technology, PIC18F4685-I/PT Datasheet
PIC18F4685-I/PT
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... PIC18F2682/2685/4682/4685 Enhanced Flash Microcontrollers with ECAN™ Technology, 10-Bit A/D © 2009 Microchip Technology Inc. Data Sheet 28/40/44-Pin and nanoWatt Technology DS39761C ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... PIC18F2682 80K 40960 PIC18F2685 96K 49152 PIC18F4682 80K 40960 PIC18F4685 96K 49152 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Peripheral Highlights: • High-Current Sink/source 25 mA/25 mA • Three External Interrupts • One Capture/Compare/PWM (CCP1) module • Enhanced Capture/Compare/PWM (ECCP1) module (40/44-pin devices only): ...
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... Pinouts are subject to change. DS39761C-page /RE3 REF REF REF RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/AN10 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN9 RB3/CANRX RB2/INT2/CANTX RB1/INT1/AN8 RB0/INT0/FLT0/AN10 RD7/PSP7/P1D RD6/PSP6/P1C RD5/PSP5/P1B RD4/PSP4/ECCP1/P1A RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3/C2IN- RD2/PSP2/C2IN+ © 2009 Microchip Technology Inc. ...
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... QFN RC7/RX/DT RD4/PSP4/ECCP1/P1A RD5/PSP5/P1B RD6/PSP6/P1C RD7/PSP7/P1D RB0/INT0/FLT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX Note: Pinouts are subject to change. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 PIC18F4682 PIC18F4685 PIC18F4682 PIC18F4685 RC0/T1OSO/T13CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI OSC2/CLKO/RA6 OSC1/CLKI/RA7 RE2/CS/AN7/C2OUT RE1/WR/AN6/C1OUT RE0/RD/AN5 RA5/AN4/SS/HLVDIN RA4/T0CKI DS39761C-page 5 ...
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... Appendix E: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 467 Appendix F: Migration from High-End to Enhanced Devices ............................................................................................................. 467 The Microchip Web Site ..................................................................................................................................................................... 481 Customer Change Notification Service .............................................................................................................................................. 481 Customer Support .............................................................................................................................................................................. 481 Reader Response .............................................................................................................................................................................. 482 PIC18F2682/2685/4682/4685 Product Identification System ............................................................................................................ 483 DS39761C-page 6 © 2009 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 DS39761C-page 7 ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 8 © 2009 Microchip Technology Inc. ...
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... DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC18F2682 • PIC18F2685 • PIC18F4682 • PIC18F4685 This family of devices offers the advantages of all PIC18 microcontrollers – namely, high performance at an economical price – with the addition of high-endurance, Enhanced Flash program memory. ...
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... Enhanced Flash memory, designated with an “F” in the part number (such as PIC18F2685), accommodate an operating V range of 4.2V to 5.5V. DD Low-voltage parts, designated by “LF” (such as PIC18LF2685), function over an extended V of 2.0V to 5.5V. © 2009 Microchip Technology Inc. devices, only on two range DD ...
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... OST), MCLR (optional), WDT WDT Yes Yes Yes Yes 75 Instructions; 83 with Extended Instruction Set Enabled Enabled 28-pin PDIP 28-pin PDIP 28-pin SOIC 28-pin SOIC PIC18F4682 PIC18F4685 DC – 40 MHz DC – 40 MHz 80K 96K 40960 49152 3328 3328 1024 1024 20 20 Ports Ports ...
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... EUSART ECAN™ 10-bit PORTA RA0/AN0 RA1/AN1 RA2/AN2/V - REF RA3/AN3/V + REF RA4/T0CKI RA5/AN4/SS/HLVDIN OSC2/CLKO/RA6 OSC1/CLKI/RA7 PORTB RB0/INT0/AN10 RB1/INT1/AN8 RB2/INT2/CANTX RB3/CANRX RB4/KBI0/AN9 RB5/KBI1/PGM RB6/KBI2/PGC RB7/KBI3/PGD PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTE (1) MCLR/V /RE3 PP © 2009 Microchip Technology Inc. ...
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... RE3 is multiplexed with MCLR and is only available when the MCLR Resets are disabled. 2: OSC1/CLKI and OSC2/CLKO are only available in select oscillator modes and when these pins are not being used as digital I/O. Refer to Section 2.0 “Oscillator Configurations” for additional information. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Data Bus<8> Data Latch ...
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... Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... T0CKI RA5/AN4/SS/HLVDIN 7 RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type PORTA is a bidirectional I/O port. I/O TTL Digital I/O. I Analog Analog input 0. I/O TTL Digital I/O ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... RC7 RX DT RE3 — Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type PORTC is a bidirectional I/O port. I/O ST Digital I/O. O — Timer1 oscillator output Timer1/Timer3 external clock input. ...
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... Crystal Oscillator mode. O — mode, OSC2 pin outputs CLKO which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. I/O TTL General purpose I/O pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... T0CKI RA5/AN4/SS/HLVDIN 7 24 RA5 AN4 SS HLVDIN RA6 RA7 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTA is a bidirectional I/O port. 19 I/O TTL Digital I/O. I Analog Analog input 0 ...
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... Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming clock pin. 17 I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP programming data pin. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... RC6 TX CK RC7/RX/ RC7 RX DT Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTC is a bidirectional I/O port. 32 I/O ST Digital I/O. O — Timer1 oscillator output. ...
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... ECCP1 PWM output B. 4 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O TTL ECCP1 PWM output C. 5 I/O ST Digital I/O. I/O TTL Parallel Slave Port data. O TTL ECCP1 PWM output D. CMOS = CMOS compatible input or output I = Input P = Power Description © 2009 Microchip Technology Inc. ...
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... 11 28 — 13 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels O = Output © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Pin Buffer Type Type TQFP PORTE is a bidirectional I/O port. 25 I/O ST Digital I/O. I TTL Read control for Parallel Slave Port (see also WR and CS pins). ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 24 © 2009 Microchip Technology Inc. ...
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... The oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 2-1: (1) C1 (1) C2 Note 1:See Table 2-1 and Table 2-2 for initial values of C1 and C2 ...
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... Clock from Ext. System EXTERNAL CLOCK INPUT OPERATION (HS OSCILLATOR CONFIGURATION) OSC1 PIC18FXXXX (HS Mode) OSC2 Open EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18FXXXX /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1/CLKI PIC18FXXXX I/O (OSC2) RA6 © 2009 Microchip Technology Inc. ...
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... Recommended values: 3 kΩ ≤ R ≤ 100 kΩ EXT C > EXT © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2.5 PLL Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from a crystal oscillator ...
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... Section 2.6.5.1 “Compensating with the EUSART”, Section 2.6.5.2 “Compensating with the Timers” and Section 2.6.5.3 “Compensating with the CCP1 Module in Capture Mode”, but other techniques may be used. or temperature changes, which can compensation techniques are © 2009 Microchip Technology Inc. ...
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... If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 ...
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... OSCTUNE<7> LP, XT, HS, RC, EC HSPLL, INTOSC/PLL Peripherals T1OSC Internal Oscillator CPU IDLEN Clock Control FOSC3:FOSC0 OSCCON<1:0> Clock Source Option for other Modules WDT, PWRT, FSCM and Two-Speed Startup © 2009 Microchip Technology Inc. ...
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... INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The IDLEN bit determines if the device goes into Sleep mode or one of the Idle modes when the SLEEP instruction is executed ...
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... Source selected by the INTSRC bit (OSCTUNE<7>), see text. 3: Default output frequency of INTOSC on Reset. DS39761C-page 32 (1) R/W-0 R R-0 IRCF0 OSTS IOFS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) (1) R/W-0 R/W-0 SCS1 SCS0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... Feedback inverter disabled at quiescent voltage level Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others) ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 34 © 2009 Microchip Technology Inc. ...
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... Note 1: IDLEN reflects its value when the SLEEP instruction is executed. 2: Includes INTOSC and INTOSC postscaler, as well as the INTRC source. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 3.1.1 CLOCK SOURCES The SCS1:SCS0 bits allow the selection of one of three clock sources for power-managed modes. They are: • ...
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... Figure 3-2). When the clock switch is complete, the T1RUN bit is cleared, the OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. © 2009 Microchip Technology Inc. ...
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... RC_RUN mode is not recommended. This mode is entered by setting SCS1 to ‘1’. Although it is ignored recommended that SCS0 also be cleared; this is to maintain software compatibility with future devices. When the clock source is switched to © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 n-1 ...
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... The INTRC source will continue to run if either the WDT or the Fail-Safe Clock Monitor is enabled n-1 n Clock Transition OST (1) (1) T PLL 1 2 n-1 n Clock Transition PC OSTS bit Set = 2 ms (approx). These intervals are not shown to scale © 2009 Microchip Technology Inc. ...
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... (approx). These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 3.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled but not yet run- ning, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result CSD © 2009 Microchip Technology Inc. ...
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... INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/ GIEH bit (INTCON< ...
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... CSD (1) INTRC (3) INTOSC T IOBST is the PLL Lock-out Timer (parameter F12 (parameter 39), the INTOSC stabilization period. IOBST Clock Ready Status Bit (OSCCON) OSTS (2) — IOFS (4) ( OSTS rc (2) — (5) IOFS (4) ( OSTS rc (2) — IOFS (4) ( OSTS rc (2) — (5) IOFS © 2009 Microchip Technology Inc. ...
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... INTRC Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin. 2: See Table 4-2 for time-out situations. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 A simplified block diagram of the on-chip Reset circuit is shown in Figure 4-1. ...
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... Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39761C-page 44 R/W-1 R-1 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (2) R/W-0 R/W-0 POR BOR bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... If these conditions are not met, the device must be held in Reset until the operating conditions are met. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 POR events are captured by the POR bit (RCON<1>). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs ...
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... BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled in software; operation controlled by SBOREN. BOR enabled in hardware in Run and Idle modes, disabled during Sleep mode. BOR enabled in hardware; must be disabled by reprogramming the Configuration bits. © 2009 Microchip Technology Inc. ...
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... INTIO1, INTIO2 66 ms Note (65.5 ms) is the nominal Power-up Timer (PWRT) delay the nominal time required for the PLL to lock. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 4.5.3 PLL LOCK TIME-OUT With the PLL enabled in its PLL mode, the time-out incorporate sequence following a Power-on Reset is slightly different from other oscillator modes ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET DS39761C-page PWRT T OST T PWRT T OST T PWRT T OST © 2009 Microchip Technology Inc RISE < PWRT ): CASE CASE 2 DD ...
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... TIME-OUT SEQUENCE ON POR w/PLL ENABLED (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. OST ≈ max. First three stages of the Power-up Timer. T PLL © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 , V RISE > PWRT T OST T PWRT T ...
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... Special Function Registers. These are categorized by Power-on and Brown-out Resets, Master Clear and WDT Resets and WDT wake-ups. RCON Register Program Counter SBOREN 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h (2) 0000h ( (1) ( STKPTR Register POR BOR STKFUL STKUNF © 2009 Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 MCLR Resets, Power-on Reset, ...
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... Microchip Technology Inc. ...
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... NOP instruction). The PIC18F2682 and PIC18F4682 each have 80 Kbytes of Flash memory and can store up to 40,960 single-word instructions. The PIC18F2685 and PIC18F4685 each have 96 Kbytes of Flash memory and can store up to 49,152 single-word instructions. PIC18 devices have two interrupt vectors. The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 TOSL 34h 00011 001A34h 00010 Top-of-Stack 000D58h 00001 00000 can return these values to Stack Pointer STKPTR<4:0> 00010 © 2009 Microchip Technology Inc. ...
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... SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 are cleared by user software POR. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 When the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero ...
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... Data is transferred to or from program memory one byte at a time. Table read and table write operations are discussed further in Section 6.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. nn ...
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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.2.2 INSTRUCTION FLOW/PIPELINING An “ ...
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... REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code 0006h is encoded in the program Word Address ↓ 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h © 2009 Microchip Technology Inc. ...
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... SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 5.3.2 “Access Bank” provides a detailed description of the Access RAM. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 5.3.1 BANK SELECT REGISTER (BSR) Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible ...
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... RAM (from Bank 0). The second 128 bytes are Special Function Registers (from Bank 15). When The BSR specifies the Bank used by the instruction. Access Bank 00h Access RAM Low 5Fh 60h Access RAM High (SFRs) FFh © 2009 Microchip Technology Inc. ...
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... Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’ © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Data Memory 000h ...
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... LATD RCSTA F8Bh LATC EEADRH F8Ah LATB EEADR F89h LATA EEDATA F88h — (3) F87h — EECON1 F86h — IPR3 F85h — (1) PIR3 F84h PORTE (1) PIE3 F83h PORTD IPR2 F82h PORTC PIR2 F81h PORTB PIE2 F80h PORTA © 2009 Microchip Technology Inc. ...
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... Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Name Address F5Fh CANCON_RO0 F3Fh ...
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... E8Bh — — E8Ah — — E89h — — E88h — — E87h — — E86h — — E85h — — E84h — — E83h — — E82h — — E81h — — E80h — © 2009 Microchip Technology Inc. ...
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... Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Name Address E6Fh CANCON_RO5 E5Fh ...
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... D91h RXF15SIDL D90h RXF15SIDH D8Fh — D8Eh — D8Dh — D8Ch — D8Bh RXF14EIDL D8Ah RXF14EIDH D89h RXF14SIDL D88h RXF14SIDH D87h RXF13EIDL D86h RXF13EIDH D85h RXF13SIDL D84h RXF13SIDH D83h RXF12EIDL D82h RXF12EIDH D81h RXF12SIDL D80h RXF12SIDH © 2009 Microchip Technology Inc. ...
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... RXF6SIDL D60h RXF6SIDH Note 1: Registers available only on PIC18F4X8X devices; otherwise, the registers read as ‘0’. 2: When any TX_ENn bit in RX_TX_SELn is set, then the corresponding bit in this register has transmit properties. 3: This is not a physical register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 DS39761C-page 77 ...
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... N/A 51, 91 N/A 51, 92 N/A 51, 92 N/A 51, 92 N/A 51, 92 ---- xxxx 51, 91 51, 91 xxxx xxxx 52, 69 ---- 0000 N/A 52, 91 N/A 52, 92 N/A 52, 92 N/A 52, 92 N/A 52, 92 52, 91 ---- xxxx 52, 91 xxxx xxxx © 2009 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 4 Bit 3 Bit 2 ...
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... RE0 ---- xxxx 54, 147 RD0 xxxx xxxx 54, 140 RC0 xxxx xxxx 54, 137 © 2009 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 4 Bit 3 Bit 2 ...
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... TXB1D11 TXB1D10 xxxx xxxx 56, 286 TXB1D01 TXB1D00 xxxx xxxx 56, 286 DLC1 DLC0 -x-- xxxx 56, 287 EID1 EID0 xxxx xxxx 56, 286 EID9 EID8 xxxx xxxx 56, 285 EID17 EID16 xxx- x-xx 56, 285 SID4 SID3 xxxx xxxx 56, 285 © 2009 Microchip Technology Inc. ...
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... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 4 Bit 3 Bit 2 ...
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... B4D40 xxxx xxxx 59, 302 B4D30 xxxx xxxx 59, 302 B4D20 xxxx xxxx 59, 302 B4D10 xxxx xxxx 59, 302 B4D00 xxxx xxxx 58, 302 DLC0 -xxx xxxx 58, 303 DLC0 -x-- xxxx 58, 304 EID0 xxxx xxxx 59, 301 EID8 xxxx xxxx 59, 301 © 2009 Microchip Technology Inc. ...
Page 85
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 4 Bit 3 Bit 2 ...
Page 86
... B0D70 xxxx xxxx 60, 302 B0D60 xxxx xxxx 60, 302 B0D50 xxxx xxxx 60, 302 B0D40 xxxx xxxx 60, 302 B0D30 xxxx xxxx 60, 302 B0D20 xxxx xxxx 60, 302 B0D10 xxxx xxxx 60, 302 B0D00 xxxx xxxx 60, 302 DLC0 -xxx xxxx 58, 303 © 2009 Microchip Technology Inc. ...
Page 87
... CAN bits have multiple functions depending on the selected mode of the CAN module. 8: This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2. 9: These registers and/or bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 4 Bit 3 Bit 2 Bit 1 — ...
Page 88
... SID3 xxxx xxxx 62, 305 EID0 xxxx xxxx 62, 306 EID8 xxxx xxxx 62, 306 EID16 xxx- x-xx 62, 305 SID3 xxxx xxxx 62, 305 EID0 xxxx xxxx 62, 306 EID8 xxxx xxxx 62, 306 EID16 xxx- x-xx 62, 305 SID3 xxxx xxxx 62, 305 © 2009 Microchip Technology Inc. ...
Page 89
... For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 It is recommended that only BCF, BSF, SWAPF, MOVFF ...
Page 90
... Example 5-5. EXAMPLE 5-5: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING LFSR FSR0, 100h ; NEXT CLRF POSTINC0 ; Clear INDF ; register then ; inc pointer BTFSS FSR0H All done with ; Bank1? BRA NEXT ; NO, clear next CONTINUE ; YES, continue © 2009 Microchip Technology Inc. ...
Page 91
... ECCh. This means the contents of location ECCh will be added to that of the W register and stored back in ECCh. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 mapped in the SFR space, but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair ...
Page 92
... Indirect Addressing. Similarly, operations by Indirect Addressing are gener- ally permitted on all other SFRs. Users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. © 2009 Microchip Technology Inc. ...
Page 93
... Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 When using the extended instruction set, this addressing mode requires the following: • ...
Page 94
... FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory BSR 000h 00000000 Bank 0 080h 100h 001001da Bank 1 through Bank 14 F00h Bank 15 F60h SFRs FFFh Data Memory © 2009 Microchip Technology Inc. 00h 60h Valid Range for ‘f’ FFh ffffffff FSR2L ffffffff ...
Page 95
... F00h BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any indirect or ...
Page 96
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 96 © 2009 Microchip Technology Inc. ...
Page 97
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 98
... The WR control bit initiates write operations. The bit cannot be cleared, only set, in software cleared in hardware at the completion of the write operation. Note: The EEIF Interrupt flag bit (PIR2<4>) is set when the write is complete. It must be cleared in software. When set, Table Latch (8-bit) TABLAT © 2009 Microchip Technology Inc. ...
Page 99
... RD bit cannot be set when EEPGD = 1 or CFGS = 1 Does not initiate an EEPROM read Note 1: When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-x R/W-0 ...
Page 100
... TBLPTR based on Flash program memory operations. Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write 8 7 TBLPTRH Table Erase/Write TBLPTR<21:6> Table Read – TBLPTR<21:0> 0 TBLPTRL Table Write TBLPTR<5:0> © 2009 Microchip Technology Inc. ...
Page 101
... TBLRD*+ MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT ...
Page 102
... TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts © 2009 Microchip Technology Inc. ...
Page 103
... Set the EECON1 register for the write operation: • set EEPGD bit to point to program memory; • clear the CFGS bit to access program memory; • set WREN to enable byte writes. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The long write is necessary for programming the internal Flash. Instruction execution is halted while in a long write cycle ...
Page 104
... TBLWT holding register. ; loop until buffers are full © 2009 Microchip Technology Inc. ...
Page 105
... CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ; point to Flash program memory ; access Flash program memory ; enable write to memory ...
Page 106
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 106 © 2009 Microchip Technology Inc. ...
Page 107
... EECON1 and EECON2. These are the same registers which control access to the program memory and are used in a similar manner for the data EEPROM. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The EECON1 register (Register 7-1) is the control register for data and program memory access. Control bit EEPGD determines if the access will be to program or data EEPROM memory ...
Page 108
... When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the error condition. DS39761C-page 108 R/W-0 R/W-x R/W-0 (1) FREE WRERR WREN U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/S-0 R/S bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 109
... BSF EECON1, WR BSF INTCON, GIE BCF EECON1, WREN © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Additionally, the WREN bit in EECON1 must be set to enable writes. This mechanism prevents accidental writes to data EEPROM due to unexpected code execution (i.e., runaway programs). The WREN bit should be kept clear at all times, except when updating the EEPROM ...
Page 110
... Loop to refresh array ; Read current address ; ; Write 55h ; ; Write 0AAh ; Set WR bit to begin write ; Wait for write to complete ; Increment address ; Not zero again ; Increment the high address ; Not zero again ; Disable writes ; Enable interrupts information (e.g., program © 2009 Microchip Technology Inc. ...
Page 111
... CMIF (1) PIE2 OSCFIE CMIE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. Note 1: These bits are available in PIC18F4682/4685 devices and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
Page 112
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 112 © 2009 Microchip Technology Inc. ...
Page 113
... Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 EXAMPLE 8-1: MOVF ARG1, W MULWF ARG2 EXAMPLE 8-2: MOVF ARG1, W MULWF ARG2 ...
Page 114
... PRODL RES1 Add cross PRODH products ; WREG ; ; ARG1H ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL PRODL RES1 Add cross PRODH products ; WREG ; ; ARG2H ARG2H:ARG2L neg? SIGN_ARG1 ; no, check ARG1 ARG1L RES2 ; ARG1H ARG1H ARG1H:ARG1L neg? CONT_CODE ; no, done ARG2L RES2 ; ARG2H © 2009 Microchip Technology Inc. ...
Page 115
... Individual interrupts can be disabled through their corresponding enable bits. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible ...
Page 116
... INT1IP INT2IF INT2IE INT2IP IPEN IPEN PEIE/GIEL IPEN TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP PEIE/GIEL GIE/GEIH INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP © 2009 Microchip Technology Inc. Wake- Sleep Mode Interrupt to CPU Vector to Location 0008h GIE/GIEH Interrupt to CPU Vector to Location 0018h ...
Page 117
... None of the RB7:RB4 pins have changed state Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Note: Interrupt flag bits are set when an interrupt ...
Page 118
... User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. DS39761C-page 118 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 R/W-1 — RBIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 119
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 ...
Page 120
... R-0 R/W-0 R/W-0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) © 2009 Microchip Technology Inc. R/W-0 R/W-0 TMR2IF TMR1IF bit Bit is unknown ...
Page 121
... Compare mode TMR1 register compare match occurred (must be cleared in software TMR1 register compare match occurred PWM mode: Unused in this mode. Note 1: These bits are available in PIC18F4682/4685 and reserved in PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 EEIF BCLIF HLVDIF U = Unimplemented bit, read as ‘ ...
Page 122
... R/W-0 R/W-0 (1) ERRIF TXBnIF TXB1IF W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 R/W-0 (1) TXB0IF RXB1IF RXB0IF R/W-0 R/W-0 R/W-0 (1) TXB0IF RXBnIF FIFOWMIF bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 123
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 TXIE SSPIE CCP1IE U = Unimplemented bit, read as ‘ ...
Page 124
... ECCP1IE: ECCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled Note 1: These bits are available on PIC18F4682/4685 devices only. DS39761C-page 124 R/W-0 R/W-0 R/W-0 EEIE BCLIE HLVDIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) (1) R/W-0 R/W-0 (1) TMR3IE ECCP1IE bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 125
... Unimplemented: Read as ‘0’ When CAN is in Mode 2: FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, these bits are forced to ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 (1) ERRIE ...
Page 126
... Low priority Note 1: This bit is reserved on PIC18F2682/2685 devices; always maintain this bit clear. DS39761C-page 126 R/W-1 R/W-1 R/W-1 TXIP SSPIP CCP1IP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) R/W-1 R/W-1 TMR2IP TMR1IP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 127
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ECCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority Note 1: These bits are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-1 R/W-1 R/W-1 EEIP BCLIP HLVDIP U = Unimplemented bit, read as ‘0’ ...
Page 128
... R/W-1 R/W-1 (1) ERRIP TXBnIP TXB1IP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared (1) (1) R/W-1 R/W-1 R/W-1 (1) TXB0IP RXB1IP RXB0IP R/W-1 R/W-1 R/W-1 (1) TXB0IP RXBnIP FIFOWMIP bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 129
... For details of bit operation, see Register 4-1. Note 1: If SBOREN is enabled, its Reset state is ‘1’; otherwise ‘0’. 2: The actual Reset value of POR is determined by the type of device Reset. See Register 4-1 for additional information. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-1 R-1 R-1 RI ...
Page 130
... Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere ; Restore BSR ; Restore WREG ; Restore STATUS © 2009 Microchip Technology Inc. ...
Page 131
... PORT Note 1: I/O pins have diode protection to V © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 10.1 PORTA, TRISA and LATA Registers PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 132
... Main oscillator input connection, determined by FOSC3:FOSC0 x Configuration bits. Enabling OSC1 overrides digital I/O. ANA Main clock input connection, determined by FOSC3:FOSC0 x Configuration bits. Enabling CLKI overrides digital I/O. DIG LATA<7> data output. 0 TTL PORTA<7> data input. 1 Description /4). OSC © 2009 Microchip Technology Inc. ...
Page 133
... Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. 2: These registers are unimplemented on PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 ...
Page 134
... Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. © 2009 Microchip Technology Inc. ...
Page 135
... IN PGD OUT IN Legend: OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL – TTL Buffer Input Note 1: This bit is unimplemented on PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TRIS Buffer DIG LATB<0> data output. 0 TTL PORTB<0> data input. Weak pull-up available only in this mode. ...
Page 136
... Bit 5 Bit 4 Bit 3 Bit 2 RB5 RB4 RB3 RB2 INT0IE RBIE TMR0IF — TMR0IP — INT2IE INT1IE — VCFG1 VCFG0 PCFG3 PCFG2 Reset Bit 1 Bit 0 Values on page RB1 RB0 INT0IF RBIF 51 — RBIP 51 INT2IF INT1IF 51 PCFG1 PCFG0 52 © 2009 Microchip Technology Inc. ...
Page 137
... TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Note Power-on Reset, these pins are configured as digital inputs ...
Page 138
... EUSART synchronous clock input. DIG LATC<7> data output. ST PORTC<7> data input. ST EUSART asynchronous data input. DIG EUSART synchronous data output – must have TRIS set to ‘1’ to enable EUSART to control the bidirectional communication. ST EUSART synchronous data input. © 2009 Microchip Technology Inc. ...
Page 139
... TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC Data Output Register TRISC PORTC Data Direction Register © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 Reset Bit 1 Bit 0 Values ...
Page 140
... EXAMPLE 10-4: INITIALIZING PORTD CLRF PORTD ; Initialize PORTD by ; clearing output ; data latches CLRF LATD ; Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs © 2009 Microchip Technology Inc. ...
Page 141
... P1D OUT DIG 0 Legend: OUT = Output Input; ANA = Analog Signal; DIG = Digital Output Schmitt Buffer Input; TTL = TTL Buffer Input © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Description LATD<0> data output. ST PORTD<0> data input. Parallel Slave Port (PSP) data output (overrides the TRIS<0> control when enabled). ...
Page 142
... These registers are available on PIC18F4682/4685 devices only. DS39761C-page 142 Bit 5 Bit 4 Bit 3 Bit 2 RD5 RD4 RD3 RD2 IBOV PSPMODE — TRISE2 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0 Reset Bit 1 Bit 0 Values on page RD1 RD0 TRISE1 TRISE0 54 53 © 2009 Microchip Technology Inc. ...
Page 143
... The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register, read and write the latched output value for PORTE. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The fourth pin of PORTE (MCLR/V only pin. Its operation is controlled by the MCLRE Configuration bit. When selected as a port pin (MCLRE = 0), it functions as a digital input only pin ...
Page 144
... TRISE1: RE1 Direction Control bit 1 = Input 0 = Output bit 0 TRISE0: RE0 Direction Control bit 1 = Input 0 = Output DS39761C-page 144 R/W-0 U-0 R/W-1 PSPMODE — TRISE2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-1 R/W-1 TRISE1 TRISE0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
Page 145
... RE3 is the only PORTE bit implemented on both PIC18F2682/2685 and PIC18F4682/4685 devices. All other bits are implemented only when PORTE is implemented (i.e., PIC18F4682/4685 devices). 3: These registers are unimplemented on PIC18F2682/2685 devices. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TRIS Buffer DIG LATE<0> data output. ...
Page 146
... Q RD PORTD RD LATD Set Interrupt Flag PSPIF (PIR1<7>) Note: I/O pins have diode protection to V PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Q RDx pin CK TTL PORTE Pins Read RD TTL Chip Select TTL CS Write TTL WR and © 2009 Microchip Technology Inc. ...
Page 147
... C2OUT C1OUT Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port. Note 1: These registers are available on PIC18F4682/4685 devices only. 2: These bits are unimplemented on PIC18F2682/2685 devices and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ...
Page 148
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 148 © 2009 Microchip Technology Inc. ...
Page 149
... Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1 ...
Page 150
... Sync with Internal TMR0L Clocks Delay There is a delay between OSC Set TMR0L TMR0IF on Overflow 8 8 Internal Data Bus Set TMR0 TMR0IF High Byte on Overflow 8 Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 151
... Legend unknown unchanged, — = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. Note 1: RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator configuration; otherwise, they are read as ‘0’. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 11.3.1 SWITCHING PRESCALER ...
Page 152
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 152 © 2009 Microchip Technology Inc. ...
Page 153
... OSC bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 A simplified block diagram of the Timer1 module is shown in Figure 12-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 12-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
Page 154
... Special Event Trigger Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer1 On/Off Set TMR1 TMR1IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 TMR1H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 155
... T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR Osc Type Freq LP 32.768 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
Page 156
... For this method to be accurate, Timer1 must operate in Asynchronous mode and the Timer1 overflow interrupt must be enabled (PIE1<0> shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times. a Special Event Trigger © 2009 Microchip Technology Inc. ...
Page 157
... Legend unknown unchanged, — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 ; Preload TMR1 register pair ; for 1 second overflow ...
Page 158
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 158 © 2009 Microchip Technology Inc. ...
Page 159
... TMR2ON: Timer2 On bit 1 = Timer2 Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 2-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide- by-16 prescale options ...
Page 160
... Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF TXIF SSPIF CCP1IF TXIE SSPIE CCP1IE TXIP SSPIP CCP1IP Set TMR2IF TMR2 Output (to PWM or MSSP) PR2 8 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 51 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 TMR2IP TMR1IP © 2009 Microchip Technology Inc. ...
Page 161
... Enables Timer3 0 = Stops Timer3 Note 1: Thess bits and the ECCP1 module are available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 A simplified block diagram of the Timer3 module is shown in Figure 14-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 14-2. ...
Page 162
... TMR3L TCCPx 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 1 Synchronize 0 Detect Sleep Input Timer3 On/Off Set TMR3 TMR3IF High Byte on Overflow 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus © 2009 Microchip Technology Inc. ...
Page 163
... T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. Note 1: These bits are unimplemented on PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 14.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h ...
Page 164
... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 164 © 2009 Microchip Technology Inc. ...
Page 165
... Compare mode; trigger special event; reset timer (TMR1 or TMR3, CCP1IF bit is set) 11xx = PWM mode Note 1: Selected by CANCAP (CIOCON<4>) bit; overrides the CCP1 input pin source. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 The CCP1 module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register ...
Page 166
... PWM) at the same time. The interactions between the two modules are summarized in Figure 15-1 and Figure 15-2. Interaction © 2009 Microchip Technology Inc. ...
Page 167
... CCP1IE or ECCP1IE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCP1IF or ECCP1IF, should also be cleared following any such change in operating mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.2.4 CCP1 PRESCALER There are four prescaler settings in Capture mode; they ...
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... Set CCP1IF T3ECCP1 and Edge Detect T3ECCP1 4 Set ECCP1IF 4 4 T3CCP1 T3ECCP1 and Edge Detect T3ECCP1 T3CCP1 TMR3H TMR3L TMR3 Enable CCPR1H CCPR1L TMR1 Enable TMR1H TMR1L TMR3H TMR3L TMR3 Enable ECCPR1H ECCPR1L TMR1 Enable TMR1H TMR1L © 2009 Microchip Technology Inc. ...
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... TMR3H TMR3L T3CCP1 Comparator ECCPR1H ECCPR1L © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 15.3.2 TIMER1/TIMER3 MODE SELECTION Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP1 module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. ...
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... Reset Bit 1 Bit 0 Values on page INT0IF RBIF 51 POR BOR 52 TMR2IP TMR1IP 54 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 (1) TMR3IP ECCP1IP 54 (1) TMR3IF ECCP1IF 54 (1) TMR3IE ECCP1IE TMR1CS TMR1ON TMR3CS TMR3ON CCP1M1 CCP1M0 ’. © 2009 Microchip Technology Inc. ...
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... A PWM output (Figure 15-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/ period). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 FIGURE 15-4: Duty Cycle TMR2 = PR2 15 ...
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... Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation. ⎛ ⎞ F OSC log ⎝ ⎠ F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... EPWM1M1 EPWM1M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: These bits or registers are available on PIC18F4682/4685 devices only. 2: The SBOREN bit is only available when CONFIG2L<1:0> = © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE ...
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... PIC18F2682/2685/4682/4685 NOTES: DS39761C-page 174 © 2009 Microchip Technology Inc. ...
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... PWM mode; P1A, P1C active-high; P1B, P1D active-low 1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high 1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 enhanced features are discussed in detail in Section 16.4 “Enhanced PWM Mode”. Capture, ...
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... The latter is more generic but will work for either single or multi-output PWM. RD4 RD5 All PIC18F4682/4685 Devices: ECCP1 RD5/PSP5 P1A P1B P1A P1B up single output PWM described in Section 15.4.4 for PWM Operation” or RD6 RD7 RD6/PSP6 RD7/PSP7 RD6/PSP6 RD7/PSP7 P1C P1D © 2009 Microchip Technology Inc. ...
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... ECCP1 pin and latch D.C. PR2 Note: The 8-bit TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register ...
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... The general relationship of the outputs in all configurations is summarized in Figure 16-2. 9.77 kHz 39.06 kHz FFh FFh OSC log F PWM bits log(2) 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 © 2009 Microchip Technology Inc. ...
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... Prescale Value) OSC • Duty Cycle = T * (ECCPR1L<7:0>:ECCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 0 Duty Cycle Period (1) Delay Delay ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ FET Driver P1A Load FET Driver P1B V- V+ FET Driver Load FET Driver V- HALF-BRIDGE PWM OUTPUT Period td (1) ( FET Driver FET Driver © 2009 Microchip Technology Inc. ...
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... P1D (1) Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTD<4>, PORTD<7> data latches. The TRISD<4>, TRISD<5>, TRISD<6> and TRISD<7> bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... Reduce PWM for a PWM period before changing directions. 2. Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. QC FET Driver FET Driver QD © 2009 Microchip Technology Inc. ...
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... All signals are shown as active-high the turn-on delay of power switch QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 (1) Period depending on the Timer2 prescaler value. The modulated P1B and OSC OSC Forward Period ...
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... R/W-0 R/W-0 PDC4 PDC3 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared / cycles, between the scheduled and actual time for a PWM OSC OSC driving). The ECCPASE bit (1) R/W-0 R/W-0 PDC2 PDC1 PDC0 bit Bit is unknown © 2009 Microchip Technology Inc. ...
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... PSSBD1:PSSBD0: Pins B and D Shutdown State Control bits 1x = Pins B and D tri-state 01 = Drive Pins B and D to ‘1’ Drive Pins B and D to ‘0’ Note 1: This register is available on PIC18F4682/4685 devices only. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 (1) R/W-0 R/W-0 R/W-0 ECCPAS0 ...
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... TMR2IF bit being set as the second PWM period begins. PWM Period Normal PWM Shutdown Shutdown Event Occurs Event Clears PWM Period Normal PWM Shutdown Event Occurs Shutdown Event Clears PWM Resumes ECCPASE Cleared by Firmware PWM Resumes © 2009 Microchip Technology Inc. ...
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... Wait until TMRx overflows (TMRxIF bit is set). • Enable the ECCP1/P1A, P1B, P1C and/or P1D pin outputs by clearing the respective TRIS bits. • Clear the ECCPASE bit (ECCP1AS<7>). © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 16.4.10 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP1 registers to their Reset states ...
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... PDC2 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 51 PD POR BOR 52 TMR2IP TMR1IP 54 TMR2IF TMR1IF 54 TMR2IE TMR1IE 54 (2) TMR3IP ECCP1IP 53 (2) TMR3IF ECCP1IF 54 (2) TMR3IE ECCP1IE TMR1CS TMR1ON 52 52 T2CKPS0 TMR3CS TMR3ON PSSBD1 PSSBD0 53 PDC1 PDC0 53 © 2009 Microchip Technology Inc. ...
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... MSSP 2 module is operating in SPI mode. Additional details are provided under the individual sections. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four ...
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... SSPIF interrupt is set. During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared © 2009 Microchip Technology Inc. R-0 R bit Bit is unknown ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 R/W-0 R/W-0 R/W-0 (2) ...
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... Example 17-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP Status register (SSPSTAT) indicates the various status conditions. © 2009 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF) Shift Register (SSPSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock ...
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... SMP bit. The time when the SSPBUF is loaded with the received data is shown. bit 5 bit 4 bit 2 bit 1 bit 3 bit 2 bit 5 bit 4 bit 3 bit Clock Modes bit 0 bit 0 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
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... SSPIF Interrupt Flag SSPSR to SSPBUF © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output ...
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... Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF DS39761C-page 196 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 2 bit 3 bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ bit 1 bit 0 bit 0 Next Q4 Cycle after Q2↓ © 2009 Microchip Technology Inc. ...
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... CKE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Note 1: These bits are unimplemented in PIC18F2682/2685 devices; always maintain these bits clear. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 17.3.9 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer ...
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... SSPBUF and the SSPIF interrupt is set. Addr Match During transmission, the SSPBUF is not double- buffered. A write to SSPBUF will write to both SSPBUF and SSPSR. Set, Reset S, P bits (SSPSTAT reg operation mode operation. The 2 C Slave mode. © 2009 Microchip Technology Inc. ...
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... This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3: ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. © 2009 Microchip Technology Inc. PIC18F2682/2685/4682/4685 2 C™ MODE) ...
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... C™ MODE) R/W-0 R/W-0 R/W-0 (1) (2) CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) /(4 * (SSPADD + 1)) OSC R/W-0 R/W-0 (2) (2) (2) SSPM1 SSPM0 bit Bit is unknown 2 C conditions were not valid for a (2) © 2009 Microchip Technology Inc. ...