PIC18F4685-I/PT Microchip Technology, PIC18F4685-I/PT Datasheet - Page 241

• Manufacturer Part Number: PIC18F4685-I/PT
• Description: IC PIC MCU FLASH 48KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4685-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 96KB (48K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3328 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 44TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT44PT3 - SOCKET TRAN ICE 44MQFP/TQFPI3-DB18F4680 - BOARD DAUGHTER ICEPIC3AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 18-7:
TABLE 18-6:
© 2009 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCON
SPBRGH
SPBRG
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Note 1:
Note:
RX (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Name
Reserved in PIC18F2682/2685 devices; always maintain these bits clear.
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
ABDOVF
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Start
ASYNCHRONOUS RECEPTION
(1)
(1)
(1)
bit
bit 0
RCIDL
ADIE
ADIP
ADIF
Bit 6
RX9
TX9
bit 1
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
—
bit 7/8
PIC18F2682/2685/4682/4685
Stop
INT0IE
bit
CREN
SYNC
SCKP
TXIE
TXIP
Bit 4
TXIF
Word 1
RCREG
Start
bit
bit 0
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
TMR0IF
CCP1IE
CCP1IP
bit 7/8
CCP1IF
Word 2
RCREG
BRGH
FERR
Bit 2
—
Stop
bit
TMR2IE
TMR2IP
TMR2IF
INT0IF
Start
OERR
TRMT
WUE
Bit 1
bit
TMR1IF
TMR1IE
TMR1IP
ABDEN
bit 7/8
RX9D
TX9D
DS39761C-page 241
RBIF
Bit 0
Stop
bit
on page
Values
Reset
51
54
54
54
53
53
53
53
53
53