EP7312-CVZ Cirrus Logic Inc, EP7312-CVZ Datasheet - Page 42

• Manufacturer Part Number: EP7312-CVZ
• Description: IC ARM720T MCU 90/74MHZ 208-LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP7r

Specifications of EP7312-CVZ

• Core Size: 32-Bit
• Core Processor: ARM7
• Speed: 74MHz
• Connectivity: Codec, DAI, EBI/EMI, IrDA, Keypad, SPI/Microwire1, UART/USART
• Peripherals: LCD, LED, MaverickKey, PWM
• Number Of I /o: 27
• Program Memory Type: ROMless
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 2.7 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-LQFP
• Controller Family/series: (ARM7)
• No. Of I/o's: 27
• Ram Memory Size: 48KB
• Cpu Speed: 74MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: SSI, UART
• Rohs Compliant: Yes
• Processor Series: EP73xx
• Core: ARM720T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB7312
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1209 - KIT DEVELOPMENT EP73XX ARM7
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1134

EP7312
High-Performance, Low-Power System on Chip
42
C20
D1
D2
D18
D19
D20
E1
E2
E3
E18
E19
E20
F1
F2
F3
F18
F19
F20
G1
G2
G3
G18
G19
G20
H1
H[2]
H[3]
H[18]
H19
H20
J1
D3
Ball Location
nPOR
PB[7]
RXD[2]
VDDIO
VSSIO
nBATCHG
A[7]
PB[4]
TXD[2]
WRITE/nSDRAS
nMEDCHG/nBROM
nEXTPWR
D[9]
PB[3]
PB[6]
TDI
D[7]
A[8]
D[10]
PB[1]
PB[2]
PB[5]
D[8]
A[9]
D[11]
PA[7]
TDO
PB[0]
A[10]
D[12]
A[12]
PA[4]
Name
Strength
with p/u*
Schmitt
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Table 21. 204-Ball TFBGA Ball Listing (Continued)
†
©
Copyright Cirrus Logic, Inc. 2005
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Reset
State
High
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
Low
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
‡
(All Rights Reserved)
Pad ground
Pad power
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
Power-on reset input
GPIO port B
UART 2 receive data input
Digital I/O power, 3.3V
I/O ground
Battery changed sense input
System byte address
GPIO port B
UART 2 transmit data output
Transfer direction / SDRAM RAS signal output
Media change interrupt input / internal ROM boot enable
External power supply sense input
Data I/O
GPIO port B
GPIO port B
JTAG data input
Data I/O
System byte address
Data I/O
GPIO port B
GPIO port B
Data I/O
System byte address
Data I/O
GPIO port A
JTAG data out
GPIO port B
System byte address
Data I/O
System byte address
GPIO port A
Description
DS508F1