Z8F0113PJ005SG Zilog, Z8F0113PJ005SG Datasheet - Page 86
Z8F0113PJ005SG
Manufacturer Part Number
Z8F0113PJ005SG
Description
IC ENCORE MCU FLASH 1K 28DIP
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F0223SB005SG.pdf
(247 pages)
Specifications of Z8F0113PJ005SG
Core Processor
Z8
Core Size
8-Bit
Speed
5MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Other names
269-3995
Z8F0113PJ005SG
Z8F0113PJ005SG
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generated and the count value in the Timer High and Low Byte registers is reset to
and counting resumes. The
interrupt is because of an input capture event.
If no Capture event occurs, the timer counts up to the 16-bit Compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the Reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001H
the timer interrupt is not caused by an input capture event.
Follow the steps below for configuring a timer for CAPTURE RESTART mode and initi-
ating the count:
1. Write to the Timer Control register to:
2. Write to the Timer High and Low Byte registers to set the starting count value
3. Write to the Timer Reload High and Low Byte registers to set the Reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000H. This allows the
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control register to enable the timer and initiate counting.
In CAPTURE mode, the elapsed time from timer start to Capture event can be calculated
using the following equation:
COMPARE Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the Compare value, the timer generates an interrupt and counting continues (the
–
–
–
–
(typically
software to determine if interrupts were generated by either a Capture or a Reload
event. If the PWM High and Low Byte registers still contain
the interrupt was generated by a Reload.
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input Capture and Reload events. If appropriate, configure the timer interrupt to be
generated only at the input Capture event or the Reload event by setting TICONFIG
field of the TxCTL1 register.
Capture Elapsed Time (s)
and counting resumes. The
Disable the timer.
Configure the timer for CAPTURE RESTART mode. Setting the mode also
involves writing to
Set the prescale value.
Set the Capture edge (rising or falling) for the Timer Input.
0001H
).
INPCAP
TMODEHI
=
INPCAP
(
------------------------------------------------------------------------------------------------- -
bit in TxCTL1 register is set to indicate the timer
Capture Value Start Value
bit in TxCTL1 register.
System Clock Frequency (Hz)
bit in TxCTL1 register is cleared to indicate
–
Z8 Encore! XP
0000H
Product Specification
) Prescale
×
after the interrupt,
®
F0823 Series
0001H
Timers
76
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