ST7FLITE29F2M6TR STMicroelectronics, ST7FLITE29F2M6TR Datasheet - Page 131

• Manufacturer Part Number: ST7FLITE29F2M6TR
• Description: IC MCU 8BIT 8K FLASH 20-SOIC
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE29F2M6TR

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: ST7FLITE2x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLIT2-COS/COM, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 7 Channel / 13 bit, 7 Channel
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17 REVISION HISTORY
Table 28. Revision History
30-August-
Date
2004
Revision
3
Updated
Added data for Fcpu @ 1MHz into
EnabledProgramming Capability for EMU3,
Reset delay in
Altered note 1 for
Removed sentence relating to an effective change only after overflow for CK[1:0],
MOD00 replaced by 0Ex in
Added Note 2 related to Exit from Active Halt,
Changed
Changed
Added illegal opcode detection to page 1,
Clarification of Flash read-out protection,
Added note 4 and description relating to Total Percentage in Error and Amplifier Output Offset
Variation to the ADC Characteristics subsection and table,
Added note 5 and description relating to Offset Variation in Temperature to ADC Characteris-
tics subsection and table,
f
Updated f
Correctedf
Max values updated for ADC Accuracy,
Socket Board development kit details added in
Notes indicating that PB4 cannot be used as an external interrupt in HALT mode,
on page 132
-Removed “optional” referring to V
-Changed FMP_R option bit description in
-Added “CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE” on page 132
PLL
value of 1MHz quoted as Typical instead of a Minimum in
Figure 62. Typical IDD in WAIT vs. fCPU
section 11.4.2 on page 71
section 11.4.3.3 on page 74
SCK
CPU
and
in
section 11.1.3 on page 53
in SLOW and SLOW WAIT modes in
section 13.10.1 on page 115
Section 8.3 PERIPHERAL INTERRUPTS
section 13.2.3 on page 94
page 120
Figure 37 on page 58
Description of Changes
DD
Section 13.4.1 Supply Current
in
Figure 5 on page 13
page 118
section 4.5.1 on page 14
changed to 30µs
section 7.6 on page
section 15.1 on page 124
Table 26
removing references to RESET
to f
section 11.2.5 on page 60
Table 27 on page 126
CPU
with correct data
section 13.4.1 on page 101
/4 and f
page 120
CPU
section 13.3.4.1 on page 97
30,
/2
table.
section 12 on page 87
ST7LITE2
section 16.6
page 61
131/133