C8051F311-GMR Silicon Laboratories Inc, C8051F311-GMR Datasheet - Page 155

IC 8051 MCU 16K FLASH 28MLP

C8051F311-GMR

Manufacturer Part Number
C8051F311-GMR
Description
IC 8051 MCU 16K FLASH 28MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F31xr
Datasheets

Specifications of C8051F311-GMR

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
25
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
17-chx10-bit
Number Of Timers
4
For Use With
336-1446 - ADAPTER PROGRAM TOOLSTICK F311336-1253 - DEV KIT FOR C8051F310/F311
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
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Manufacturer:
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ARBLOST
MASTER
TXMODE
ACKRQ
STO
ACK
STA
Bit
SI
• A START is generated.
• START is generated.
• SMB0DAT is written before the start of an
• A START followed by an address byte is
• A STOP is detected while addressed as a
• Arbitration is lost due to a detected STOP.
• A byte has been received and an ACK
• A repeated START is detected as a MASTER
• SCL is sensed low while attempting to gener-
• SDA is sensed low while transmitting a ‘1’
• The incoming ACK value is low (ACKNOWL-
• A START has been generated.
• Lost arbitration.
• A byte has been transmitted and an
• A byte has been received.
• A START or repeated START followed by a
• A STOP has been received.
Table 14.3. Sources for Hardware Changes to SMB0CN
SMBus frame.
received.
slave.
response value is needed.
when STA is low (unwanted repeated START).
ate a STOP or repeated START condition.
(excluding ACK bits).
EDGE).
ACK/NACK received.
slave address + R/W has been received.
Set by Hardware When...
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
• A STOP is generated.
• Arbitration is lost.
• A START is detected.
• Arbitration is lost.
• SMB0DAT is not written before the
• Must be cleared by software.
• A pending STOP is generated.
• After each ACK cycle.
• Each time SI is cleared.
• The incoming ACK value is high (NOT
• Must be cleared by software.
start of an SMBus frame.
ACKNOWLEDGE).
Cleared by Hardware When...
155

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