C8051F504-IQ Silicon Laboratories Inc, C8051F504-IQ Datasheet - Page 144

• Manufacturer Part Number: C8051F504-IQ
• Description: IC 8051 MCU 32K FLASH 48-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFP
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1518

C8051F50x/F51x
SFR Definition 17.1. VDM0CN: V
SFR Address = 0xFF; SFR Page = 0x00
17.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 5.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
17.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the value specified in Table 5.4, “Reset Electrical Characteristics,”
on page 46, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
144
Name
Reset
4:0
Bit
Type
7
6
5
Bit
VDDSTAT
VDMLVL
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 17.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source. See Table 5.4 for the minimum V
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
V
0: V
1: V
tem includes code that writes to and/or erases Flash.
Read = 00000b; Write = Don’t care.
Varies
DD
DD
DD
R
6
DD
DD
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Level Select.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Monitor Threshold is set to VRST-LOW
Monitor Threshold is set to VRST-HIGH. This setting is required for any sys-
VDMLVL
R/W
5
0
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Rev. 1.2
DD
R
4
0
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
R
3
0
DD
DD
Monitor turn-on time.
R
2
0
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
R
1
0
R
0
0