MC9S12XET256CAG Freescale Semiconductor, MC9S12XET256CAG Datasheet - Page 163

• Manufacturer Part Number: MC9S12XET256CAG
• Description: MCU 16BIT 256K FLASH 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XET256CAG

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 119
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Processor Series: S12XE
• Core: HCS12
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1. Read: Anytime.
1. Read: Anytime.
2.3.76
2.3.77
Freescale Semiconductor
PER1AD0
Function
Address 0x0277
Address 0x0278
PT0AD1
Write: Anytime.
Write: Anytime.
Altern.
Field
Field
Reset
Reset
7-0
7-0
W
W
R
R
PER1AD07
PT0AD17
Port AD0 pull device enable—Enable pull devices on input pins
These bits configure whether a pull device is activated, if the associated pin is used as an input. This bit has no effect
if the pin is used as an output. Out of reset no pull device is enabled.
1 Pull device enabled.
0 Pull device disabled.
Port AD1 general purpose input/output data—Data Register
This register is associated with ATD1 analog inputs AN[15:8] on PAD[31:24], respectively.
When not used with the alternative function, this pin can be used as general purpose I/O.
If the associated data direction bits of these pins are set to 1, a read returns the value of the port register, otherwise
the buffered pin input state is read.
AN15
Port AD0 Pull Up Enable Register 1 (PER1AD0)
Port AD1 Data Register 0 (PT0AD1)
0
0
7
7
PER1AD06
PT0AD16
Figure 2-74. Port AD0 Pull Up Enable Register 1 (PER1AD0)
AN14
0
0
6
6
Table 2-72. PER1AD0 Register Field Descriptions
Figure 2-75. Port AD1 Data Register 0 (PT0AD1)
Table 2-73. PT0AD1 Register Field Descriptions
MC9S12XE-Family Reference Manual , Rev. 1.23
PER1AD05
PT0AD15
AN13
0
0
5
5
PER1AD04
PT0AD14
AN12
0
0
4
4
Description
Description
PER1AD03
PT0AD13
AN11
3
0
3
0
Chapter 2 Port Integration Module (S12XEPIMV1)
PER1AD02
PT0AD12
AN10
0
0
2
2
PER1AD01
PT0AD11
Access: User read/write
Access: User read/write
AN9
0
0
1
1
PER1AD00
PT0AD10
AN8
0
0
0
0
163
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