M30281F6HP#U5B Renesas Electronics America, M30281F6HP#U5B Datasheet - Page 232

• Manufacturer Part Number: M30281F6HP#U5B
• Description: IC M16C/28 MCU FLASH 48K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30281F6HP#U5B

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 55
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 64-LQFP
• For Use With: R0K330290S000BE - KIT EVAL STARTER FOR M16C/29M30290T2-CPE - EMULATOR COMPACT M16C/26A/28/29M30290T2-CPE-HP - EMULATOR COMPACT FOR M16C/TINY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
1
. v
Figure 14.32 SIM Interface Connection
Figure 14.33 Parity Error Signal Output Timing
J
6
0
C
2
9
Figure 14.32 shows the example of connecting the SIM interface. Connect T
pull-up.
0 .
2 /
B
14.1.6.1 Parity Error Signal Output
0
0
8
0
The parity error signal is enabled by setting the U2ERE bit in theU2C1 register to “1”.
• When receiving
The parity error signal is output when a parity error is detected while receiving data. This is achieved
by pulling the TxD2 output low with the timing shown in Figure 14.33. If the R2RB register is read
while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output
is returned high.
• When transmitting
A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse
that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be
determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service
routine.
4
G
J
7
NOTES:
a
U2C1 register
This timing diagram applies to the case where the direct format is
implemented.
o r
0 -
. n
u
2
1. The output of microcomputer is in the high-impedance state
3
p
0
, 1
0
(pulled up externally).
(
Transfer
M
2
0
1
RxD
RI bit
TxD
clock
0
6
7
C
2 /
2
2
page 210
, 8
“H”
“H”
“H”
“L”
“L”
“L”
“1”
“0”
M
1
6
C
Microcomputer
f o
2 /
8
3
) B
8
ST
5
RxD
TxD
D0
2
2
D1
D2
D3
(1)
D4
SIM card
D5
D6
D7
X
P
D
ST : Start bit
P : Even Parity
SP : Stop bit
2
and R
SP
X
D
2
14. Serial I/O
and apply