MC68331CEH25 Freescale Semiconductor, MC68331CEH25 Datasheet - Page 52

• Manufacturer Part Number: MC68331CEH25
• Description: IC MCU 32BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: M683xxr

Specifications of MC68331CEH25

• Core Processor: CPU32
• Core Size: 32-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: ROMless
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Controller Family/series: 68K
• No. Of I/o's: 18
• Cpu Speed: 25MHz
• No. Of Timers: 1
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 2
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Data Bus Width: 32 bit
• Data Ram Size: 80 B
• Interface Type: QSPI, SCI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Eeprom Size: -
• Ram Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

5.2 Pin Function
52
Y = M111, where M is the logic state of the module mapping (MM) bit in the SIMCR
The following table is a summary of the functions of the QSM pins when they are not configured for gen-
eral-purpose I/O. The QSM data direction register (DDRQS) designates each pin except RXD as an in-
put or output.
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S/U
S
S
S
QSPI Pins
SCI Pins
$YFFC20–
$YFFD00–
$YFFD20–
$YFFD40–
$YFFC0A
$YFFC0C
$YFFC0E
$YFFC1A
$YFFC1C
$YFFC1E
$YFFCFF
$YFFC00
$YFFC02
$YFFC04
$YFFC06
$YFFC08
$YFFC10
$YFFC12
$YFFC14
$YFFC16
$YFFC18
$YFFD1F
$YFFD3F
$YFFD4F
Address
Freescale Semiconductor, Inc.
For More Information On This Product,
PCS0/SSMaster
15
PQS PIN ASSIGNMENT (PQSPAR)
PCS[3:1]
QSM INTERRUPT LEVEL (QILR)
MISO
MOSI
SCK
RXD
Table 22 QSM Address Map
TXD
Pin
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SPI CONTROL 3 (SPCR3)
NOT USED
QSM MODULE CONFIGURATION (QSMCR)
Transmit
Receive
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
COMMAND RAM (CR[0:F])
SCI CONTROL 0 (SCCR0)
SCI CONTROL 1 (SCCR1)
SPI CONTROL 0 (SPCR0)
SPI CONTROL 1 (SPCR1)
SPI CONTROL 2 (SPCR2)
TRANSMIT RAM (TR[0:F])
RECEIVE RAM (RR[0:F])
SCI STATUS (SCSR)
QSM TEST (QTEST)
SCI DATA (SCDR)
NOT USED
NOT USED
NOT USED
NOT USED
Serial Data Input to QSPI
Serial Data Output from QSPI
Serial Data Output from QSPI
Serial Data Input to QSPI
Clock Output from QSPI
Clock Input to QSPI
Input: Assertion Causes Mode Fault
Output: Selects Peripherals
Input: Selects the QSPI
Output: Selects Peripherals
None
Serial Data Output from SCI
Serial Data Input to SCI
8 7
QSM INTERRUPT VECTOR (QIVR)
PQS DATA DIRECTION (DDRQS)
PQS DATA (PORTQS)
SPI STATUS (SPSR)
Pin Function
MC68331TS/D
0