MC68HC11K1CFUE3 Freescale Semiconductor, MC68HC11K1CFUE3 Datasheet - Page 50
MC68HC11K1CFUE3
Manufacturer Part Number
MC68HC11K1CFUE3
Description
MCU 8-BIT 768 RAM 3MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Specifications of MC68HC11K1CFUE3
Core Processor
HC11
Core Size
8-Bit
Speed
3MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Type
ROMless
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SCI, SPI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
37
Number Of Timers
8
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC11K1CFUE3
Manufacturer:
FREESCALE
Quantity:
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Part Number:
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Central Processor Unit (CPU)
3.3.5 Program Counter (PC)
3.3.6 Condition Code Register (CCR)
3.3.6.1 Carry/Borrow (C)
3.3.6.2 Overflow (V)
3.3.6.3 Zero (Z)
Technical Data
50
The 16-bit program counter contains the address of the next instruction
to be executed. Its initial value after reset is fetched from one of six
possible vectors, depending on operating mode and the cause of reset,
as described in
This 8-bit register contains:
Most instructions update condition codes automatically, as described in
the following paragraphs. Certain instructions, such as pushes, pulls,
add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions
do not affect the condition codes.
codes are affected by each instruction.
The C bit is set if the CPU performs a carry or borrow during an
arithmetic operation. This bit also acts as an error flag for multiply and
divide operations. Shift and rotate instructions operate with and through
the carry bit to facilitate multiple-word shift operations.
The overflow bit is set if an operation results in a two’s complement
overflow of the 8-bit signed range –128 to +127. Otherwise, the V bit is
cleared.
The Z bit is set if the result of an arithmetic, logic, or data manipulation
operation is 0. Otherwise, the Z bit is cleared. Compare instructions do
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Five condition code indicators (C, V, Z, N, and H)
Two interrupt masking bits (IRQ and XIRQ)
A stop disable bit (S)
Central Processor Unit (CPU)
Go to: www.freescale.com
5.3 Sources of
Resets.
Table 3-1
shows which condition
M68HC11K Family
MOTOROLA
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