MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 113

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-2
9.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals on the MCU. The
system clocks are generated from an incoming clock, CGMOUT, as shown in
come from either an external oscillator or from the on-chip PLL. (See
(CGM)).
9.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output (CGMXCLK) divided by four
or the PLL output (CGMVCLK) divided by four. (See
Freescale Semiconductor
OSC1
shows the internal signal names used in this chapter.
PLL
Signal Name
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
CGMVCLK
CGMXCLK
CGMVCLK
CGMOUT
PORRST
IRST
R/W
IAB
IDB
MONITOR MODE
SELECT
CIRCUIT
CLOCK
USER MODE
BCS
CGM
Table 9-2. Signal Name Conventions
Buffered Version of OSC1 from Clock Generator Module (CGM)
PLL Output
PLL-Based or OSC1-Based Clock Output from CGM Module
(Bus Clock = CGMOUT Divided by Two)
Internal Address Bus
Internal Data Bus
Signal from the Power-On Reset Module to the SIM
Internal Reset Signal
Read/Write Signal
PTC3
Figure 9-3. CGM Clock Signals
÷
2
A
B S*
*When S = 1,
CGMOUT = B
Chapter 10 Clock Generator Module
CGMXCLK
Description
CGMOUT
Chapter 10 Clock Generator Module
SIM Bus Clock Control and Generation
÷
SIM COUNTER
Figure
2
SIM
9-3. This clock can
GENERATORS
BUS CLOCK
(CGM)).
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