MC908AZ60AVFUE Freescale Semiconductor, MC908AZ60AVFUE Datasheet - Page 211

• Manufacturer Part Number: MC908AZ60AVFUE
• Description: IC MCU 61K FLASH 8.4MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AVFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.5.3 Transmission Format When CPHA = 1
Figure 19-5
as a replacement for data sheet parametric information. Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted as a master or slave timing
diagram since the serial clock (SCK), master in/slave out (MISO), and master out/slave in (MOSI) pins
are directly connected between the master and the slave. The MISO signal is the output from the slave,
and the MOSI signal is the output from the master. The SS line is the slave select input to the slave. The
slave SPI drives its MISO output only when its slave select input (SS) is low, so that only the selected
slave drives to the master. The SS pin of the master is not shown but is assumed to be inactive. The SS
pin of the master must be high or must be reconfigured as general-purpose I/O not affecting the SPI. (See
19.6.2 Mode Fault
edge. Therefore, the slave uses the first SPSCK edge as a start transmission signal. The SS pin can
remain low between transmissions. This format may be preferable in systems having only one master and
only one slave driving the MISO data line.
19.5.4 Transmission Initiation Latency
When the SPI is configured as a master (SPMSTR = 1), transmissions are started by a software write to
the SPDR ($0012). CPHA has no effect on the delay to the start of the transmission, but it does affect the
initial state of the SCK signal. When CPHA = 0, the SCK signal remains inactive for the first half of the
first SCK cycle. When CPHA = 1, the first SCK cycle begins with an edge on the SCK line from its inactive
to its active level. The SPI clock rate (selected by SPR1–SPR0) affects the delay from the write to SPDR
and the start of the SPI transmission. (See
free-running derivative of the internal MCU clock. It is only enabled when both the SPE and SPMSTR bits
(SPCR) are set to conserve power. SCK edges occur half way through the low time of the internal MCU
clock. Since the SPI clock is free-running, it is uncertain where the write to the SPDR will occur relative
to the slower SCK. This uncertainty causes the variation in the initiation delay shown in
Freescale Semiconductor
CAPTURE STROBE
FOR REFERENCE
FROM MASTER
SCK CPOL = 0
SCK CYCLE #
SCK CPOL =1
FROM SLAVE
SS TO SLAVE
shows an SPI transmission in which CPHA (SPCR) is logic 1. The figure should not be used
MOSI
MISO
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
Error). When CPHA = 1, the master begins driving its MOSI pin on the first SPSCK
Figure 19-5. Transmission Format (CPHA = 1)
MSB
MSB
1
BIT 6
BIT 6
2
Figure
BIT 5
BIT 5
3
19-6). The internal SPI clock in the master is a
BIT 4
BIT 4
4
BIT 3
BIT 3
5
BIT 2
BIT 2
6
BIT 1
BIT 1
7
Transmission Formats
Figure
LSB
8
LSB
19-6. This
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