PIC16C74-04/L Microchip Technology, PIC16C74-04/L Datasheet - Page 141

• Manufacturer Part Number: PIC16C74-04/L
• Description: MICRO CTRL 4K 4MHZ OTP 44PLCC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-04/L

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 44-PLCC
• For Use With: DVA16XL441 - ADAPTER DEVICE ICE 44PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

14.5
The PIC16C7X family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
17). The latency is the same for one or two cycle
1997 Microchip Technology Inc.
Note:
Interrupts
Applicable Devices
72 73 73A 74 74A 76 77
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
instructions. Individual interrupt flag bits are set regard-
less of the status of their corresponding mask bit or the
GIE bit.
LOOP BCF
Note:
BTFSC INTCON, GIE
GOTO
:
For the PIC16C73/74, if an interrupt occurs
while the Global Interrupt Enable (GIE) bit
is being cleared, the GIE bit may uninten-
tionally be re-enabled by the user’s Inter-
rupt
instruction). The events that would cause
this to occur are:
1.
2.
3.
Perform the following to ensure that inter-
rupts are globally disabled:
INTCON, GIE
LOOP
an interrupt is acknowledged.
vector and executes the Interrupt Ser-
vice Routine.
pletes with the execution of the RET-
FIE instruction. This causes the GIE
bit to be set (enables interrupts), and
the program returns to the instruction
after the one which was meant to dis-
able interrupts.
An instruction clears the GIE bit while
The program branches to the Interrupt
The Interrupt Service Routine com-
Service
PIC16C7X
Routine
; Disable global
;
; Global interrupt
;
; NO, try again
;
;
;
interrupt bit
disabled?
Yes, continue
with program
flow
DS30390E-page 141
(the
RETFIE