PIC16C84-04I/SO Microchip Technology, PIC16C84-04I/SO Datasheet - Page 11

• Manufacturer Part Number: PIC16C84-04I/SO
• Description: IC MIC CTL EEPM 1K 4MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

4.0
There are two memory blocks in the PIC16C84. These
are the program memory and the data memory. Each
block has its own bus, so that access to each block can
occur during the same oscillator cycle.
The data memory can further be broken down into the
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly mapped
into the data memory, but is indirectly mapped. That is
an indirect address pointer specifies the address of the
data EEPROM memory to read/write. The 64 bytes of
data EEPROM memory have the address range
0h-3Fh. More details on the EEPROM memory can be
found in Section 7.0.
4.1
The PIC16CXX has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. For
the PIC16C84, only the first 1K x 14 (0000h-03FFh) are
physically implemented (Figure 4-1). Accessing a loca-
tion above the physically implemented address will
cause a wraparound. For example, locations 20h,
420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h
will be the same instruction.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
1997 Microchip Technology Inc.
MEMORY ORGANIZATION
Program Memory Organization
FIGURE 4-1: PROGRAM MEMORY MAP
CALL, RETURN
RETFIE, RETLW
Peripheral Interrupt Vector
AND STACK
Stack Level 1
Stack Level 8
Reset Vector
PC<12:0>
PIC16C84
13
DS30445C-page 11
1FFFh
0000h
0004h
3FFh