PIC16C84-04I/SO Microchip Technology, PIC16C84-04I/SO Datasheet - Page 25

• Manufacturer Part Number: PIC16C84-04I/SO
• Description: IC MIC CTL EEPM 1K 4MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-04I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

6.0
The Timer0 module timer/counter has the following
features:
• 8-bit timer/counter
• Readable and writable
• 8-bit software programmable prescaler
• Internal or external clock select
• Interrupt on overflow from FFh to 00h
• Edge select for external clock
Timer mode is selected by clearing the T0CS bit
(OPTION<5>). In timer mode, the Timer0 module
(Figure 6-1) will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
increment is inhibited for the following two cycles
(Figure 6-2 and Figure 6-3). The user can work around
this by writing an adjusted value to the TMR0 register.
Counter mode is selected by setting the T0CS bit
(OPTION<5>). In this mode TMR0 will increment either
on every rising or falling edge of pin RA4/T0CKI. The
incrementing edge is determined by the T0 source
FIGURE 6-1:
FIGURE 6-2:
RA4/T0CKI
1997 Microchip Technology Inc.
Instruction
Instruction
Executed
Note 1: Bits T0CS, T0SE, PS2, PS1, PS0 and PSA are located in the OPTION register.
pin
TMR0
Fetch
PC
TIMER0 MODULE AND TMR0
REGISTER
2: The prescaler is shared with the Watchdog Timer (Figure 6-6)
T0SE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
T0
F
TMR0 BLOCK DIAGRAM
TMR0 TIMING: INTERNAL CLOCK/NO PRESCALER
OSC
PC-1
/4
MOVWF TMR0
T0+1
T0CS
PC
0
1
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Write TMR0
executed
T0+2
PS2, PS1, PS0
Programmable
PC+1
Prescaler
3
NT0
Read TMR0
reads NT0
PC+2
PSA
1
0
selects the rising edge. Restrictions on the external
6.1
The TMR0 interrupt is generated when the TMR0
register overflows from FFh to 00h. This overflow sets
the T0IF bit (INTCON<2>). The interrupt can be
masked by clearing enable bit T0IE (INTCON<5>). The
T0IF bit must be cleared in software by the Timer0
Module interrupt service routine before re-enabling this
interrupt. The TMR0 interrupt (Figure 6-4) cannot wake
the processor from SLEEP since the timer is shut off
during SLEEP.
edge select bit, T0SE (OPTION<4>). Clearing bit T0SE
clock input are discussed in detail in Section 6.2.
The prescaler is shared between the Timer0 Module
and the Watchdog Timer. The prescaler assignment is
controlled,
(OPTION<3>). Clearing bit PSA will assign the
prescaler to the Timer0 Module. The prescaler is not
readable or writable. When the prescaler (Section 6.3)
is assigned to the Timer0 Module, the prescale value
(1:2, 1:4, ..., 1:256) is software selectable.
PSout
Read TMR0
reads NT0
NT0
PC+3
(2 cycle delay)
Sync with
TMR0 Interrupt
Internal
clocks
in
MOVF TMR0,W
Read TMR0
reads NT0
NT0
PC+4
software,
PSout
TMR0 register
MOVF TMR0,W
Read TMR0
reads NT0 + 1
NT0+1
PIC16C84
Data bus
PC+5
by
control
8
DS30445C-page 25
Read TMR0
reads NT0 + 2
on Overflow
Set bit T0IF
NT0+2
PC+6
bit
PSA
T0