PIC16C84-10I/SO Microchip Technology, PIC16C84-10I/SO Datasheet - Page 101

• Manufacturer Part Number: PIC16C84-10I/SO
• Description: MICRO CTL EEPM 1K 10MHZ IT18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C84-10I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 10MHz
• Peripherals: POR, WDT
• Number Of I /o: 13
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: EEPROM
• Eeprom Size: 64 x 8
• Ram Size: 36 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Data Converters: -
• Connectivity: -

APPENDIX E: CONVERSION CONSIDERATIONS - PIC16C84 TO PIC16F83/F84 AND
Considerations for converting from the PIC16C84 to
the PIC16F84 are listed in the table below. These con-
siderations apply to converting from the PIC16C84 to
the PIC16F83 (same as PIC16F84 except for program
The polarity of the PWRTE bit has
been reversed. Ensure that the pro-
grammer has this bit correctly set
before programming.
The PIC16F84 (and PIC16CR84)
have larger RAM sizes. Ensure that
this does not cause an issue with
your program.
The MCLR pin now has an on-chip
filter. The input signal on the MCLR
pin will require a longer low pulse to
generate an interrupt.
Some electrical specifications have
been improved (see I
Compare the electrical specifica-
tions of the two devices to ensure
that this will not cause a compatibil-
ity issue.
PORTA and crystal oscillator values
less than 500kHz
RB0/INT pin
EEADR<7:6> and I
Code Protect
Recommended value of R
RC oscillator circuits
GIE bit unintentional enable
1997 Microchip Technology Inc.
Difference
PIC16CR83/CR84
DD
PD
example).
EXT
for
PWRTE
RAM = 36 bytes
MCLR pulse width (low)
= 350ns; 2.0V
= 150ns; 3.0V
I
I
=100 A (PIC16C84)
=100 A (PIC16LC84)
For crystal oscillator configurations
operating below 500kHz, the device
may generate a spurious internal Q-
clock when PORTA<0> switches
state.
TTL
It is recommended that the
EEADR<7:6> bits be cleared.
When either of these bits is set, the
maximum I
higher than when both are cleared.
1 CP bit
R
If an interrupt occurs while the Glo-
bal Interrupt Enable (GIE) bit is
being cleared, the GIE bit may unin-
tentionally be re-enabled by the
user’s Interrupt Service Routine (the
RETFIE instruction).
PD
PD
EXT
(typ @ 2V) = 26 A
(max @ 4V, WDT disabled)
= 3k - 100k
DD
PIC16C84
for the device is
V
V
DD
DD
and data RAM memory sizes) and the PIC16CR84 and
PIC16CR83 (ROM versions of Flash devices). Devel-
opment Systems support is available for all of the
PIC16X8X devices.
3.0V
6.0V
PWRTE
RAM = 68 bytes
MCLR pulse width (low)
= 1000ns; 2.0V
I
I
=14 A (PIC16F84)
=7 A (PIC16LF84)
N/A
TTL/ST*
(* This buffer is a Schmitt Trigger
input when configured as the exter-
nal interrupt.)
N/A
9 CP bits
R
N/A
PD
PD
EXT
(typ @ 2V) < 1 A
(max @ 4V, WDT disabled)
= 5k - 100k
PIC16C84
PIC16F84
V
DS30445C-page 101
DD
6.0V