AT90S2323-10SC Atmel, AT90S2323-10SC Datasheet - Page 31

• Manufacturer Part Number: AT90S2323-10SC
• Description: MCU 2K FLASH 10MHZ 8-SOIC
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2323-10SC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 3
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Watchdog Timer Control
Register – WDTCR
1004D–09/01
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will
not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.
Refer to the description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is set (one) the Watchdog Timer is enabled and if the WDE is cleared
(zero) the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit is set (one). To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
2. Within the next four clock cycles, write a logical “0” to WDE. This disables the
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 11.
Table 11. Watchdog Timer Prescale Select
Note:
Bit
$21 ($41)
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
be written to WDE even though it is set to “1” before the disable operation starts.
Watchdog.
The frequency of the Watchdog oscillator is voltage-dependent as shown in the Electrical
Characteristics section.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start counting from zero.
To avoid unintentional MCU resets, the Watchdog Timer should be disabled or reset
before changing the Watchdog Timer Prescale Select.
WDP1
0
0
1
1
0
0
1
1
R
7
–
0
WDP0
0
1
0
1
0
1
0
1
R
6
–
0
Number of WDT
Oscillator Cycles
16K cycles
32K cycles
64K cycles
128K cycles
256K cycles
512K cycles
1,024K cycles
2,048K cycles
R
5
–
0
WDTOE
R/W
4
0
Typical Time-out
at V
47 ms
94 ms
0.19 s
0.38 s
0.75 s
1.5 s
3.0 s
6.0 s
WDE
R/W
AT90S/LS2323/2343
3
0
CC
= 3.0V
WDP2
R/W
2
0
WDP1
R/W
1
0
Typical Time-out
at V
15 ms
30 ms
60 ms
0.12 s
0.24 s
0.49 s
0.97 s
1.9 s
CC
WDP0
R/W
0
0
= 5.0V
WDTCR
31